forked from OSchip/llvm-project
104 lines
3.7 KiB
LLVM
104 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -O0 -mcpu=skx | FileCheck %s
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define i32 @_Z3foov() {
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; CHECK-LABEL: _Z3foov:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: pushl %ebx
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; CHECK-NEXT: .Lcfi0:
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: subl $24, %esp
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; CHECK-NEXT: .Lcfi1:
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .Lcfi2:
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; CHECK-NEXT: .cfi_offset %ebx, -8
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; CHECK-NEXT: movb $1, %al
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; CHECK-NEXT: movw $10959, {{[0-9]+}}(%esp) # imm = 0x2ACF
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; CHECK-NEXT: movw $-15498, {{[0-9]+}}(%esp) # imm = 0xC376
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; CHECK-NEXT: movw $19417, {{[0-9]+}}(%esp) # imm = 0x4BD9
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; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: cmpw $0, {{[0-9]+}}(%esp)
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; CHECK-NEXT: kmovb %eax, %k0
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; CHECK-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
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; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%esp) # 2-byte Spill
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; CHECK-NEXT: jne .LBB0_2
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; CHECK-NEXT: # BB#1: # %lor.rhs
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: movb %al, %cl
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; CHECK-NEXT: kmovb %ecx, %k0
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; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%esp) # 2-byte Spill
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; CHECK-NEXT: jmp .LBB0_2
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; CHECK-NEXT: .LBB0_2: # %lor.end
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; CHECK-NEXT: kmovw {{[0-9]+}}(%esp), %k0 # 2-byte Reload
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; CHECK-NEXT: movb $1, %al
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; CHECK-NEXT: kmovw %k0, %ecx
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; CHECK-NEXT: andl $1, %ecx
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx # 4-byte Reload
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; CHECK-NEXT: subl %ecx, %edx
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; CHECK-NEXT: setl %ah
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; CHECK-NEXT: # implicit-def: %ECX
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; CHECK-NEXT: movb %ah, %cl
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; CHECK-NEXT: andl $1, %ecx
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; CHECK-NEXT: kmovw %ecx, %k0
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; CHECK-NEXT: kmovb %k0, %ebx
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; CHECK-NEXT: andb $1, %bl
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; CHECK-NEXT: movzbl %bl, %ecx
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; CHECK-NEXT: xorl $-1, %ecx
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; CHECK-NEXT: cmpl $0, %ecx
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; CHECK-NEXT: kmovb %eax, %k0
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; CHECK-NEXT: movl %edx, {{[0-9]+}}(%esp) # 4-byte Spill
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; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%esp) # 2-byte Spill
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; CHECK-NEXT: jne .LBB0_4
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; CHECK-NEXT: # BB#3: # %lor.rhs4
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: movb %al, %cl
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; CHECK-NEXT: kmovb %ecx, %k0
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; CHECK-NEXT: kmovw %k0, {{[0-9]+}}(%esp) # 2-byte Spill
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; CHECK-NEXT: jmp .LBB0_4
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; CHECK-NEXT: .LBB0_4: # %lor.end5
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; CHECK-NEXT: kmovw {{[0-9]+}}(%esp), %k0 # 2-byte Reload
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; CHECK-NEXT: kmovw %k0, %eax
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; CHECK-NEXT: andl $1, %eax
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; CHECK-NEXT: movw %ax, %cx
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; CHECK-NEXT: movw %cx, {{[0-9]+}}(%esp)
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; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: addl $24, %esp
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; CHECK-NEXT: popl %ebx
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; CHECK-NEXT: retl
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entry:
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%aa = alloca i16, align 2
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%bb = alloca i16, align 2
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%cc = alloca i16, align 2
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store i16 10959, i16* %aa, align 2
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store i16 -15498, i16* %bb, align 2
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store i16 19417, i16* %cc, align 2
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%0 = load i16, i16* %aa, align 2
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%conv = zext i16 %0 to i32
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%1 = load i16, i16* %cc, align 2
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%tobool = icmp ne i16 %1, 0
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br i1 %tobool, label %lor.end, label %lor.rhs
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lor.rhs: ; preds = %entry
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br label %lor.end
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lor.end: ; preds = %lor.rhs, %entry
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%2 = phi i1 [ true, %entry ], [ false, %lor.rhs ]
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%conv1 = zext i1 %2 to i32
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%cmp = icmp slt i32 %conv, %conv1
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%conv2 = zext i1 %cmp to i32
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%neg = xor i32 %conv2, -1
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%tobool3 = icmp ne i32 %neg, 0
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br i1 %tobool3, label %lor.end5, label %lor.rhs4
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lor.rhs4: ; preds = %lor.end
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br label %lor.end5
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lor.end5: ; preds = %lor.rhs4, %lor.end
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%3 = phi i1 [ true, %lor.end ], [ false, %lor.rhs4 ]
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%conv6 = zext i1 %3 to i16
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store i16 %conv6, i16* %bb, align 2
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%4 = load i16, i16* %bb, align 2
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%conv7 = zext i16 %4 to i32
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ret i32 %conv7
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}
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