forked from OSchip/llvm-project
efe7f5ede0
Introduce `Vec` records, each bundling all information related to a single SIMD lane interpretation. This lets TableGen definitions take a single Vec parameter from which they can extract information rather than taking multiple redundant parameters. This commit refactors all of the SIMD load and store instruction definitions to use the new `Vec`s. Subsequent commits will similarly refactor additional instruction definitions. Differential Revision: https://reviews.llvm.org/D93660 |
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CMakeLists.txt | ||
WebAssemblyAsmBackend.cpp | ||
WebAssemblyFixupKinds.h | ||
WebAssemblyInstPrinter.cpp | ||
WebAssemblyInstPrinter.h | ||
WebAssemblyMCAsmInfo.cpp | ||
WebAssemblyMCAsmInfo.h | ||
WebAssemblyMCCodeEmitter.cpp | ||
WebAssemblyMCTargetDesc.cpp | ||
WebAssemblyMCTargetDesc.h | ||
WebAssemblyTargetStreamer.cpp | ||
WebAssemblyTargetStreamer.h | ||
WebAssemblyWasmObjectWriter.cpp |