forked from OSchip/llvm-project
176 lines
4.6 KiB
LLVM
176 lines
4.6 KiB
LLVM
; RUN: opt %s -analyze -divergence -use-gpu-divergence-analysis | FileCheck %s
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target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
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target triple = "nvptx64-nvidia-cuda"
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; return (n < 0 ? a + threadIdx.x : b + threadIdx.x)
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define i32 @no_diverge(i32 %n, i32 %a, i32 %b) {
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; CHECK-LABEL: Printing analysis 'Legacy Divergence Analysis' for function 'no_diverge'
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entry:
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%tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
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%cond = icmp slt i32 %n, 0
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br i1 %cond, label %then, label %else ; uniform
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; CHECK-NOT: DIVERGENT: br i1 %cond,
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then:
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%a1 = add i32 %a, %tid
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br label %merge
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else:
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%b2 = add i32 %b, %tid
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br label %merge
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merge:
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%c = phi i32 [ %a1, %then ], [ %b2, %else ]
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ret i32 %c
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}
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; c = a;
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; if (threadIdx.x < 5) // divergent: data dependent
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; c = b;
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; return c; // c is divergent: sync dependent
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define i32 @sync(i32 %a, i32 %b) {
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; CHECK-LABEL: Printing analysis 'Legacy Divergence Analysis' for function 'sync'
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bb1:
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%tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.y()
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%cond = icmp slt i32 %tid, 5
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br i1 %cond, label %bb2, label %bb3
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; CHECK: DIVERGENT: br i1 %cond,
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bb2:
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br label %bb3
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bb3:
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%c = phi i32 [ %a, %bb1 ], [ %b, %bb2 ] ; sync dependent on tid
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; CHECK: DIVERGENT: %c =
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ret i32 %c
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}
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; c = 0;
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; if (threadIdx.x >= 5) { // divergent
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; c = (n < 0 ? a : b); // c here is uniform because n is uniform
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; }
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; // c here is divergent because it is sync dependent on threadIdx.x >= 5
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; return c;
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define i32 @mixed(i32 %n, i32 %a, i32 %b) {
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; CHECK-LABEL: Printing analysis 'Legacy Divergence Analysis' for function 'mixed'
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bb1:
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%tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.z()
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%cond = icmp slt i32 %tid, 5
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br i1 %cond, label %bb6, label %bb2
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; CHECK: DIVERGENT: br i1 %cond,
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bb2:
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%cond2 = icmp slt i32 %n, 0
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br i1 %cond2, label %bb4, label %bb3
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bb3:
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br label %bb5
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bb4:
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br label %bb5
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bb5:
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%c = phi i32 [ %a, %bb3 ], [ %b, %bb4 ]
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; CHECK-NOT: DIVERGENT: %c =
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br label %bb6
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bb6:
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%c2 = phi i32 [ 0, %bb1], [ %c, %bb5 ]
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; CHECK: DIVERGENT: %c2 =
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ret i32 %c2
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}
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; We conservatively treats all parameters of a __device__ function as divergent.
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define i32 @device(i32 %n, i32 %a, i32 %b) {
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; CHECK-LABEL: Printing analysis 'Legacy Divergence Analysis' for function 'device'
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; CHECK: DIVERGENT: i32 %n
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; CHECK: DIVERGENT: i32 %a
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; CHECK: DIVERGENT: i32 %b
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entry:
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%cond = icmp slt i32 %n, 0
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br i1 %cond, label %then, label %else
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; CHECK: DIVERGENT: br i1 %cond,
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then:
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br label %merge
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else:
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br label %merge
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merge:
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%c = phi i32 [ %a, %then ], [ %b, %else ]
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ret i32 %c
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}
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; int i = 0;
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; do {
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; i++; // i here is uniform
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; } while (i < laneid);
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; return i == 10 ? 0 : 1; // i here is divergent
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;
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; The i defined in the loop is used outside.
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define i32 @loop() {
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; CHECK-LABEL: Printing analysis 'Legacy Divergence Analysis' for function 'loop'
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entry:
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%laneid = call i32 @llvm.nvvm.read.ptx.sreg.laneid()
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br label %loop
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loop:
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%i = phi i32 [ 0, %entry ], [ %i1, %loop ]
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; CHECK-NOT: DIVERGENT: %i =
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%i1 = add i32 %i, 1
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%exit_cond = icmp sge i32 %i1, %laneid
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br i1 %exit_cond, label %loop_exit, label %loop
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loop_exit:
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%cond = icmp eq i32 %i, 10
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br i1 %cond, label %then, label %else
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; CHECK: DIVERGENT: br i1 %cond,
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then:
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ret i32 0
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else:
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ret i32 1
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}
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; Same as @loop, but the loop is in the LCSSA form.
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define i32 @lcssa() {
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; CHECK-LABEL: Printing analysis 'Legacy Divergence Analysis' for function 'lcssa'
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entry:
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%tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
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br label %loop
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loop:
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%i = phi i32 [ 0, %entry ], [ %i1, %loop ]
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; CHECK-NOT: DIVERGENT: %i =
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%i1 = add i32 %i, 1
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%exit_cond = icmp sge i32 %i1, %tid
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br i1 %exit_cond, label %loop_exit, label %loop
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loop_exit:
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%i.lcssa = phi i32 [ %i, %loop ]
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; CHECK: DIVERGENT: %i.lcssa =
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%cond = icmp eq i32 %i.lcssa, 10
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br i1 %cond, label %then, label %else
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; CHECK: DIVERGENT: br i1 %cond,
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then:
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ret i32 0
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else:
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ret i32 1
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}
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; Verifies sync-dependence is computed correctly in the absense of loops.
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define i32 @sync_no_loop(i32 %arg) {
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entry:
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%0 = add i32 %arg, 1
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%tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
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%1 = icmp sge i32 %tid, 10
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br i1 %1, label %bb1, label %bb2
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bb1:
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br label %bb3
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bb2:
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br label %bb3
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bb3:
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%2 = add i32 %0, 2
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; CHECK-NOT: DIVERGENT: %2
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ret i32 %2
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}
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declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
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declare i32 @llvm.nvvm.read.ptx.sreg.tid.y()
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declare i32 @llvm.nvvm.read.ptx.sreg.tid.z()
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declare i32 @llvm.nvvm.read.ptx.sreg.laneid()
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!nvvm.annotations = !{!0, !1, !2, !3, !4}
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!0 = !{i32 (i32, i32, i32)* @no_diverge, !"kernel", i32 1}
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!1 = !{i32 (i32, i32)* @sync, !"kernel", i32 1}
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!2 = !{i32 (i32, i32, i32)* @mixed, !"kernel", i32 1}
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!3 = !{i32 ()* @loop, !"kernel", i32 1}
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!4 = !{i32 (i32)* @sync_no_loop, !"kernel", i32 1}
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