forked from OSchip/llvm-project
94 lines
4.6 KiB
TableGen
94 lines
4.6 KiB
TableGen
//===- Mips.td - Describe the Mips Target Machine ----------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This is the top level entry point for the Mips target.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// Register File, Calling Conv, Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "MipsRegisterInfo.td"
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include "MipsSchedule.td"
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include "MipsInstrInfo.td"
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include "MipsCallingConv.td"
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def MipsInstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// Mips Subtarget features //
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//===----------------------------------------------------------------------===//
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def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
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"General Purpose Registers are 64-bit wide.">;
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def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
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"Support 64-bit FP registers.">;
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def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
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"true", "Only supports single precision float">;
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def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32",
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"Enable o32 ABI">;
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def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI",
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"Enable eabi ABI">;
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def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
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"true", "Enable vector FPU instructions.">;
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def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true",
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"Enable 'signext in register' instructions.">;
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def FeatureCondMov : SubtargetFeature<"condmov", "HasCondMov", "true",
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"Enable 'conditional move' instructions.">;
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def FeatureMulDivAdd : SubtargetFeature<"muldivadd", "HasMulDivAdd", "true",
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"Enable 'multiply add/sub' instructions.">;
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def FeatureMinMax : SubtargetFeature<"minmax", "HasMinMax", "true",
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"Enable 'min/max' instructions.">;
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def FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true",
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"Enable 'byte/half swap' instructions.">;
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def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true",
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"Enable 'count leading bits' instructions.">;
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def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
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"Mips1 ISA Support">;
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def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
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"Mips2 ISA Support">;
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def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
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"Mips32 ISA Support",
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[FeatureCondMov, FeatureBitCount]>;
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def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
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"Mips32r2", "Mips32r2 ISA Support",
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[FeatureMips32, FeatureSEInReg]>;
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//===----------------------------------------------------------------------===//
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// Mips processors supported.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, MipsGenericItineraries, Features>;
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def : Proc<"mips1", [FeatureMips1]>;
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def : Proc<"r2000", [FeatureMips1]>;
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def : Proc<"r3000", [FeatureMips1]>;
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def : Proc<"mips2", [FeatureMips2]>;
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def : Proc<"r6000", [FeatureMips2]>;
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def : Proc<"4ke", [FeatureMips32r2]>;
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// Allegrex is a 32bit subset of r4000, both for interger and fp registers,
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// but much more similar to Mips2 than Mips3. It also contains some of
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// Mips32/Mips32r2 instructions and a custom vector fpu processor.
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def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureEABI,
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FeatureVFPU, FeatureSEInReg, FeatureCondMov, FeatureMulDivAdd,
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FeatureMinMax, FeatureSwap, FeatureBitCount]>;
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def Mips : Target {
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let InstructionSet = MipsInstrInfo;
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}
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