forked from OSchip/llvm-project
1055 lines
38 KiB
C++
1055 lines
38 KiB
C++
//===- TailDuplicator.cpp - Duplicate blocks into predecessors' tails -----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This utility class duplicates basic blocks ending in unconditional branches
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// into the tails of their predecessors.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/TailDuplicator.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/DenseSet.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Analysis/ProfileSummaryInfo.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
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#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineSizeOpts.h"
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#include "llvm/CodeGen/MachineSSAUpdater.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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#include <algorithm>
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#include <cassert>
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#include <iterator>
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#include <utility>
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using namespace llvm;
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#define DEBUG_TYPE "tailduplication"
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STATISTIC(NumTails, "Number of tails duplicated");
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STATISTIC(NumTailDups, "Number of tail duplicated blocks");
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STATISTIC(NumTailDupAdded,
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"Number of instructions added due to tail duplication");
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STATISTIC(NumTailDupRemoved,
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"Number of instructions removed due to tail duplication");
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STATISTIC(NumDeadBlocks, "Number of dead blocks removed");
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STATISTIC(NumAddedPHIs, "Number of phis added");
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// Heuristic for tail duplication.
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static cl::opt<unsigned> TailDuplicateSize(
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"tail-dup-size",
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cl::desc("Maximum instructions to consider tail duplicating"), cl::init(2),
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cl::Hidden);
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static cl::opt<unsigned> TailDupIndirectBranchSize(
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"tail-dup-indirect-size",
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cl::desc("Maximum instructions to consider tail duplicating blocks that "
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"end with indirect branches."), cl::init(20),
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cl::Hidden);
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static cl::opt<bool>
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TailDupVerify("tail-dup-verify",
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cl::desc("Verify sanity of PHI instructions during taildup"),
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cl::init(false), cl::Hidden);
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static cl::opt<unsigned> TailDupLimit("tail-dup-limit", cl::init(~0U),
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cl::Hidden);
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void TailDuplicator::initMF(MachineFunction &MFin, bool PreRegAlloc,
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const MachineBranchProbabilityInfo *MBPIin,
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MBFIWrapper *MBFIin,
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ProfileSummaryInfo *PSIin,
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bool LayoutModeIn, unsigned TailDupSizeIn) {
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MF = &MFin;
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TII = MF->getSubtarget().getInstrInfo();
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TRI = MF->getSubtarget().getRegisterInfo();
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MRI = &MF->getRegInfo();
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MMI = &MF->getMMI();
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MBPI = MBPIin;
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MBFI = MBFIin;
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PSI = PSIin;
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TailDupSize = TailDupSizeIn;
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assert(MBPI != nullptr && "Machine Branch Probability Info required");
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LayoutMode = LayoutModeIn;
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this->PreRegAlloc = PreRegAlloc;
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}
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static void VerifyPHIs(MachineFunction &MF, bool CheckExtra) {
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for (MachineBasicBlock &MBB : llvm::drop_begin(MF)) {
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SmallSetVector<MachineBasicBlock *, 8> Preds(MBB.pred_begin(),
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MBB.pred_end());
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MachineBasicBlock::iterator MI = MBB.begin();
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while (MI != MBB.end()) {
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if (!MI->isPHI())
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break;
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for (MachineBasicBlock *PredBB : Preds) {
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bool Found = false;
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for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) {
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MachineBasicBlock *PHIBB = MI->getOperand(i + 1).getMBB();
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if (PHIBB == PredBB) {
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Found = true;
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break;
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}
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}
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if (!Found) {
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dbgs() << "Malformed PHI in " << printMBBReference(MBB) << ": "
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<< *MI;
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dbgs() << " missing input from predecessor "
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<< printMBBReference(*PredBB) << '\n';
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llvm_unreachable(nullptr);
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}
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}
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for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2) {
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MachineBasicBlock *PHIBB = MI->getOperand(i + 1).getMBB();
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if (CheckExtra && !Preds.count(PHIBB)) {
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dbgs() << "Warning: malformed PHI in " << printMBBReference(MBB)
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<< ": " << *MI;
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dbgs() << " extra input from predecessor "
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<< printMBBReference(*PHIBB) << '\n';
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llvm_unreachable(nullptr);
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}
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if (PHIBB->getNumber() < 0) {
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dbgs() << "Malformed PHI in " << printMBBReference(MBB) << ": "
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<< *MI;
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dbgs() << " non-existing " << printMBBReference(*PHIBB) << '\n';
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llvm_unreachable(nullptr);
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}
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}
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++MI;
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}
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}
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}
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/// Tail duplicate the block and cleanup.
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/// \p IsSimple - return value of isSimpleBB
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/// \p MBB - block to be duplicated
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/// \p ForcedLayoutPred - If non-null, treat this block as the layout
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/// predecessor, instead of using the ordering in MF
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/// \p DuplicatedPreds - if non-null, \p DuplicatedPreds will contain a list of
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/// all Preds that received a copy of \p MBB.
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/// \p RemovalCallback - if non-null, called just before MBB is deleted.
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bool TailDuplicator::tailDuplicateAndUpdate(
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bool IsSimple, MachineBasicBlock *MBB,
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MachineBasicBlock *ForcedLayoutPred,
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SmallVectorImpl<MachineBasicBlock*> *DuplicatedPreds,
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function_ref<void(MachineBasicBlock *)> *RemovalCallback,
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SmallVectorImpl<MachineBasicBlock *> *CandidatePtr) {
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// Save the successors list.
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SmallSetVector<MachineBasicBlock *, 8> Succs(MBB->succ_begin(),
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MBB->succ_end());
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SmallVector<MachineBasicBlock *, 8> TDBBs;
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SmallVector<MachineInstr *, 16> Copies;
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if (!tailDuplicate(IsSimple, MBB, ForcedLayoutPred,
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TDBBs, Copies, CandidatePtr))
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return false;
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++NumTails;
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SmallVector<MachineInstr *, 8> NewPHIs;
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MachineSSAUpdater SSAUpdate(*MF, &NewPHIs);
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// TailBB's immediate successors are now successors of those predecessors
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// which duplicated TailBB. Add the predecessors as sources to the PHI
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// instructions.
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bool isDead = MBB->pred_empty() && !MBB->hasAddressTaken();
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if (PreRegAlloc)
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updateSuccessorsPHIs(MBB, isDead, TDBBs, Succs);
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// If it is dead, remove it.
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if (isDead) {
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NumTailDupRemoved += MBB->size();
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removeDeadBlock(MBB, RemovalCallback);
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++NumDeadBlocks;
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}
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// Update SSA form.
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if (!SSAUpdateVRs.empty()) {
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for (unsigned i = 0, e = SSAUpdateVRs.size(); i != e; ++i) {
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unsigned VReg = SSAUpdateVRs[i];
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SSAUpdate.Initialize(VReg);
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// If the original definition is still around, add it as an available
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// value.
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MachineInstr *DefMI = MRI->getVRegDef(VReg);
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MachineBasicBlock *DefBB = nullptr;
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if (DefMI) {
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DefBB = DefMI->getParent();
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SSAUpdate.AddAvailableValue(DefBB, VReg);
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}
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// Add the new vregs as available values.
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DenseMap<Register, AvailableValsTy>::iterator LI =
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SSAUpdateVals.find(VReg);
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for (unsigned j = 0, ee = LI->second.size(); j != ee; ++j) {
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MachineBasicBlock *SrcBB = LI->second[j].first;
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Register SrcReg = LI->second[j].second;
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SSAUpdate.AddAvailableValue(SrcBB, SrcReg);
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}
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// Rewrite uses that are outside of the original def's block.
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MachineRegisterInfo::use_iterator UI = MRI->use_begin(VReg);
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// Only remove instructions after loop, as DBG_VALUE_LISTs with multiple
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// uses of VReg may invalidate the use iterator when erased.
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SmallPtrSet<MachineInstr *, 4> InstrsToRemove;
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while (UI != MRI->use_end()) {
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MachineOperand &UseMO = *UI;
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MachineInstr *UseMI = UseMO.getParent();
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++UI;
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if (UseMI->isDebugValue()) {
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// SSAUpdate can replace the use with an undef. That creates
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// a debug instruction that is a kill.
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// FIXME: Should it SSAUpdate job to delete debug instructions
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// instead of replacing the use with undef?
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InstrsToRemove.insert(UseMI);
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continue;
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}
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if (UseMI->getParent() == DefBB && !UseMI->isPHI())
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continue;
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SSAUpdate.RewriteUse(UseMO);
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}
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for (auto *MI : InstrsToRemove)
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MI->eraseFromParent();
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}
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SSAUpdateVRs.clear();
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SSAUpdateVals.clear();
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}
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// Eliminate some of the copies inserted by tail duplication to maintain
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// SSA form.
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for (unsigned i = 0, e = Copies.size(); i != e; ++i) {
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MachineInstr *Copy = Copies[i];
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if (!Copy->isCopy())
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continue;
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Register Dst = Copy->getOperand(0).getReg();
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Register Src = Copy->getOperand(1).getReg();
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if (MRI->hasOneNonDBGUse(Src) &&
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MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) {
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// Copy is the only use. Do trivial copy propagation here.
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MRI->replaceRegWith(Dst, Src);
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Copy->eraseFromParent();
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}
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}
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if (NewPHIs.size())
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NumAddedPHIs += NewPHIs.size();
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if (DuplicatedPreds)
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*DuplicatedPreds = std::move(TDBBs);
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return true;
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}
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/// Look for small blocks that are unconditionally branched to and do not fall
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/// through. Tail-duplicate their instructions into their predecessors to
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/// eliminate (dynamic) branches.
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bool TailDuplicator::tailDuplicateBlocks() {
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bool MadeChange = false;
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if (PreRegAlloc && TailDupVerify) {
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LLVM_DEBUG(dbgs() << "\n*** Before tail-duplicating\n");
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VerifyPHIs(*MF, true);
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}
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for (MachineBasicBlock &MBB :
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llvm::make_early_inc_range(llvm::drop_begin(*MF))) {
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if (NumTails == TailDupLimit)
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break;
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bool IsSimple = isSimpleBB(&MBB);
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if (!shouldTailDuplicate(IsSimple, MBB))
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continue;
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MadeChange |= tailDuplicateAndUpdate(IsSimple, &MBB, nullptr);
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}
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if (PreRegAlloc && TailDupVerify)
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VerifyPHIs(*MF, false);
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return MadeChange;
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}
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static bool isDefLiveOut(Register Reg, MachineBasicBlock *BB,
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const MachineRegisterInfo *MRI) {
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for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
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if (UseMI.isDebugValue())
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continue;
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if (UseMI.getParent() != BB)
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return true;
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}
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return false;
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}
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static unsigned getPHISrcRegOpIdx(MachineInstr *MI, MachineBasicBlock *SrcBB) {
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for (unsigned i = 1, e = MI->getNumOperands(); i != e; i += 2)
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if (MI->getOperand(i + 1).getMBB() == SrcBB)
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return i;
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return 0;
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}
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// Remember which registers are used by phis in this block. This is
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// used to determine which registers are liveout while modifying the
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// block (which is why we need to copy the information).
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static void getRegsUsedByPHIs(const MachineBasicBlock &BB,
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DenseSet<Register> *UsedByPhi) {
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for (const auto &MI : BB) {
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if (!MI.isPHI())
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break;
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for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
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Register SrcReg = MI.getOperand(i).getReg();
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UsedByPhi->insert(SrcReg);
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}
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}
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}
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/// Add a definition and source virtual registers pair for SSA update.
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void TailDuplicator::addSSAUpdateEntry(Register OrigReg, Register NewReg,
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MachineBasicBlock *BB) {
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DenseMap<Register, AvailableValsTy>::iterator LI =
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SSAUpdateVals.find(OrigReg);
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if (LI != SSAUpdateVals.end())
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LI->second.push_back(std::make_pair(BB, NewReg));
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else {
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AvailableValsTy Vals;
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Vals.push_back(std::make_pair(BB, NewReg));
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SSAUpdateVals.insert(std::make_pair(OrigReg, Vals));
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SSAUpdateVRs.push_back(OrigReg);
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}
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}
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/// Process PHI node in TailBB by turning it into a copy in PredBB. Remember the
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/// source register that's contributed by PredBB and update SSA update map.
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void TailDuplicator::processPHI(
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MachineInstr *MI, MachineBasicBlock *TailBB, MachineBasicBlock *PredBB,
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DenseMap<Register, RegSubRegPair> &LocalVRMap,
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SmallVectorImpl<std::pair<Register, RegSubRegPair>> &Copies,
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const DenseSet<Register> &RegsUsedByPhi, bool Remove) {
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Register DefReg = MI->getOperand(0).getReg();
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unsigned SrcOpIdx = getPHISrcRegOpIdx(MI, PredBB);
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assert(SrcOpIdx && "Unable to find matching PHI source?");
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Register SrcReg = MI->getOperand(SrcOpIdx).getReg();
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unsigned SrcSubReg = MI->getOperand(SrcOpIdx).getSubReg();
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const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
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LocalVRMap.insert(std::make_pair(DefReg, RegSubRegPair(SrcReg, SrcSubReg)));
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// Insert a copy from source to the end of the block. The def register is the
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// available value liveout of the block.
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Register NewDef = MRI->createVirtualRegister(RC);
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Copies.push_back(std::make_pair(NewDef, RegSubRegPair(SrcReg, SrcSubReg)));
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if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg))
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addSSAUpdateEntry(DefReg, NewDef, PredBB);
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if (!Remove)
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return;
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// Remove PredBB from the PHI node.
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MI->RemoveOperand(SrcOpIdx + 1);
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MI->RemoveOperand(SrcOpIdx);
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if (MI->getNumOperands() == 1)
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MI->eraseFromParent();
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}
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/// Duplicate a TailBB instruction to PredBB and update
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/// the source operands due to earlier PHI translation.
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void TailDuplicator::duplicateInstruction(
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MachineInstr *MI, MachineBasicBlock *TailBB, MachineBasicBlock *PredBB,
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DenseMap<Register, RegSubRegPair> &LocalVRMap,
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const DenseSet<Register> &UsedByPhi) {
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// Allow duplication of CFI instructions.
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if (MI->isCFIInstruction()) {
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BuildMI(*PredBB, PredBB->end(), PredBB->findDebugLoc(PredBB->begin()),
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TII->get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(
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MI->getOperand(0).getCFIIndex());
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return;
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}
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MachineInstr &NewMI = TII->duplicate(*PredBB, PredBB->end(), *MI);
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if (PreRegAlloc) {
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for (unsigned i = 0, e = NewMI.getNumOperands(); i != e; ++i) {
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MachineOperand &MO = NewMI.getOperand(i);
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if (!MO.isReg())
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continue;
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Register Reg = MO.getReg();
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if (!Register::isVirtualRegister(Reg))
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continue;
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if (MO.isDef()) {
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const TargetRegisterClass *RC = MRI->getRegClass(Reg);
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Register NewReg = MRI->createVirtualRegister(RC);
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MO.setReg(NewReg);
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LocalVRMap.insert(std::make_pair(Reg, RegSubRegPair(NewReg, 0)));
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if (isDefLiveOut(Reg, TailBB, MRI) || UsedByPhi.count(Reg))
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addSSAUpdateEntry(Reg, NewReg, PredBB);
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} else {
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auto VI = LocalVRMap.find(Reg);
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if (VI != LocalVRMap.end()) {
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// Need to make sure that the register class of the mapped register
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// will satisfy the constraints of the class of the register being
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// replaced.
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auto *OrigRC = MRI->getRegClass(Reg);
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auto *MappedRC = MRI->getRegClass(VI->second.Reg);
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const TargetRegisterClass *ConstrRC;
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if (VI->second.SubReg != 0) {
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ConstrRC = TRI->getMatchingSuperRegClass(MappedRC, OrigRC,
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VI->second.SubReg);
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if (ConstrRC) {
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// The actual constraining (as in "find appropriate new class")
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// is done by getMatchingSuperRegClass, so now we only need to
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// change the class of the mapped register.
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MRI->setRegClass(VI->second.Reg, ConstrRC);
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}
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} else {
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// For mapped registers that do not have sub-registers, simply
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// restrict their class to match the original one.
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ConstrRC = MRI->constrainRegClass(VI->second.Reg, OrigRC);
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}
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if (ConstrRC) {
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// If the class constraining succeeded, we can simply replace
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// the old register with the mapped one.
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MO.setReg(VI->second.Reg);
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// We have Reg -> VI.Reg:VI.SubReg, so if Reg is used with a
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// sub-register, we need to compose the sub-register indices.
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MO.setSubReg(TRI->composeSubRegIndices(MO.getSubReg(),
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VI->second.SubReg));
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} else {
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// The direct replacement is not possible, due to failing register
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// class constraints. An explicit COPY is necessary. Create one
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// that can be reused
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auto *NewRC = MI->getRegClassConstraint(i, TII, TRI);
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if (NewRC == nullptr)
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NewRC = OrigRC;
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Register NewReg = MRI->createVirtualRegister(NewRC);
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BuildMI(*PredBB, NewMI, NewMI.getDebugLoc(),
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TII->get(TargetOpcode::COPY), NewReg)
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.addReg(VI->second.Reg, 0, VI->second.SubReg);
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LocalVRMap.erase(VI);
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LocalVRMap.insert(std::make_pair(Reg, RegSubRegPair(NewReg, 0)));
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MO.setReg(NewReg);
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// The composed VI.Reg:VI.SubReg is replaced with NewReg, which
|
|
// is equivalent to the whole register Reg. Hence, Reg:subreg
|
|
// is same as NewReg:subreg, so keep the sub-register index
|
|
// unchanged.
|
|
}
|
|
// Clear any kill flags from this operand. The new register could
|
|
// have uses after this one, so kills are not valid here.
|
|
MO.setIsKill(false);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/// After FromBB is tail duplicated into its predecessor blocks, the successors
|
|
/// have gained new predecessors. Update the PHI instructions in them
|
|
/// accordingly.
|
|
void TailDuplicator::updateSuccessorsPHIs(
|
|
MachineBasicBlock *FromBB, bool isDead,
|
|
SmallVectorImpl<MachineBasicBlock *> &TDBBs,
|
|
SmallSetVector<MachineBasicBlock *, 8> &Succs) {
|
|
for (MachineBasicBlock *SuccBB : Succs) {
|
|
for (MachineInstr &MI : *SuccBB) {
|
|
if (!MI.isPHI())
|
|
break;
|
|
MachineInstrBuilder MIB(*FromBB->getParent(), MI);
|
|
unsigned Idx = 0;
|
|
for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
|
|
MachineOperand &MO = MI.getOperand(i + 1);
|
|
if (MO.getMBB() == FromBB) {
|
|
Idx = i;
|
|
break;
|
|
}
|
|
}
|
|
|
|
assert(Idx != 0);
|
|
MachineOperand &MO0 = MI.getOperand(Idx);
|
|
Register Reg = MO0.getReg();
|
|
if (isDead) {
|
|
// Folded into the previous BB.
|
|
// There could be duplicate phi source entries. FIXME: Should sdisel
|
|
// or earlier pass fixed this?
|
|
for (unsigned i = MI.getNumOperands() - 2; i != Idx; i -= 2) {
|
|
MachineOperand &MO = MI.getOperand(i + 1);
|
|
if (MO.getMBB() == FromBB) {
|
|
MI.RemoveOperand(i + 1);
|
|
MI.RemoveOperand(i);
|
|
}
|
|
}
|
|
} else
|
|
Idx = 0;
|
|
|
|
// If Idx is set, the operands at Idx and Idx+1 must be removed.
|
|
// We reuse the location to avoid expensive RemoveOperand calls.
|
|
|
|
DenseMap<Register, AvailableValsTy>::iterator LI =
|
|
SSAUpdateVals.find(Reg);
|
|
if (LI != SSAUpdateVals.end()) {
|
|
// This register is defined in the tail block.
|
|
for (unsigned j = 0, ee = LI->second.size(); j != ee; ++j) {
|
|
MachineBasicBlock *SrcBB = LI->second[j].first;
|
|
// If we didn't duplicate a bb into a particular predecessor, we
|
|
// might still have added an entry to SSAUpdateVals to correcly
|
|
// recompute SSA. If that case, avoid adding a dummy extra argument
|
|
// this PHI.
|
|
if (!SrcBB->isSuccessor(SuccBB))
|
|
continue;
|
|
|
|
Register SrcReg = LI->second[j].second;
|
|
if (Idx != 0) {
|
|
MI.getOperand(Idx).setReg(SrcReg);
|
|
MI.getOperand(Idx + 1).setMBB(SrcBB);
|
|
Idx = 0;
|
|
} else {
|
|
MIB.addReg(SrcReg).addMBB(SrcBB);
|
|
}
|
|
}
|
|
} else {
|
|
// Live in tail block, must also be live in predecessors.
|
|
for (unsigned j = 0, ee = TDBBs.size(); j != ee; ++j) {
|
|
MachineBasicBlock *SrcBB = TDBBs[j];
|
|
if (Idx != 0) {
|
|
MI.getOperand(Idx).setReg(Reg);
|
|
MI.getOperand(Idx + 1).setMBB(SrcBB);
|
|
Idx = 0;
|
|
} else {
|
|
MIB.addReg(Reg).addMBB(SrcBB);
|
|
}
|
|
}
|
|
}
|
|
if (Idx != 0) {
|
|
MI.RemoveOperand(Idx + 1);
|
|
MI.RemoveOperand(Idx);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/// Determine if it is profitable to duplicate this block.
|
|
bool TailDuplicator::shouldTailDuplicate(bool IsSimple,
|
|
MachineBasicBlock &TailBB) {
|
|
// When doing tail-duplication during layout, the block ordering is in flux,
|
|
// so canFallThrough returns a result based on incorrect information and
|
|
// should just be ignored.
|
|
if (!LayoutMode && TailBB.canFallThrough())
|
|
return false;
|
|
|
|
// Don't try to tail-duplicate single-block loops.
|
|
if (TailBB.isSuccessor(&TailBB))
|
|
return false;
|
|
|
|
// Set the limit on the cost to duplicate. When optimizing for size,
|
|
// duplicate only one, because one branch instruction can be eliminated to
|
|
// compensate for the duplication.
|
|
unsigned MaxDuplicateCount;
|
|
bool OptForSize = MF->getFunction().hasOptSize() ||
|
|
llvm::shouldOptimizeForSize(&TailBB, PSI, MBFI);
|
|
if (TailDupSize == 0)
|
|
MaxDuplicateCount = TailDuplicateSize;
|
|
else
|
|
MaxDuplicateCount = TailDupSize;
|
|
if (OptForSize)
|
|
MaxDuplicateCount = 1;
|
|
|
|
// If the block to be duplicated ends in an unanalyzable fallthrough, don't
|
|
// duplicate it.
|
|
// A similar check is necessary in MachineBlockPlacement to make sure pairs of
|
|
// blocks with unanalyzable fallthrough get layed out contiguously.
|
|
MachineBasicBlock *PredTBB = nullptr, *PredFBB = nullptr;
|
|
SmallVector<MachineOperand, 4> PredCond;
|
|
if (TII->analyzeBranch(TailBB, PredTBB, PredFBB, PredCond) &&
|
|
TailBB.canFallThrough())
|
|
return false;
|
|
|
|
// If the target has hardware branch prediction that can handle indirect
|
|
// branches, duplicating them can often make them predictable when there
|
|
// are common paths through the code. The limit needs to be high enough
|
|
// to allow undoing the effects of tail merging and other optimizations
|
|
// that rearrange the predecessors of the indirect branch.
|
|
|
|
bool HasIndirectbr = false;
|
|
if (!TailBB.empty())
|
|
HasIndirectbr = TailBB.back().isIndirectBranch();
|
|
|
|
if (HasIndirectbr && PreRegAlloc)
|
|
MaxDuplicateCount = TailDupIndirectBranchSize;
|
|
|
|
// Check the instructions in the block to determine whether tail-duplication
|
|
// is invalid or unlikely to be profitable.
|
|
unsigned InstrCount = 0;
|
|
for (MachineInstr &MI : TailBB) {
|
|
// Non-duplicable things shouldn't be tail-duplicated.
|
|
// CFI instructions are marked as non-duplicable, because Darwin compact
|
|
// unwind info emission can't handle multiple prologue setups. In case of
|
|
// DWARF, allow them be duplicated, so that their existence doesn't prevent
|
|
// tail duplication of some basic blocks, that would be duplicated otherwise.
|
|
if (MI.isNotDuplicable() &&
|
|
(TailBB.getParent()->getTarget().getTargetTriple().isOSDarwin() ||
|
|
!MI.isCFIInstruction()))
|
|
return false;
|
|
|
|
// Convergent instructions can be duplicated only if doing so doesn't add
|
|
// new control dependencies, which is what we're going to do here.
|
|
if (MI.isConvergent())
|
|
return false;
|
|
|
|
// Do not duplicate 'return' instructions if this is a pre-regalloc run.
|
|
// A return may expand into a lot more instructions (e.g. reload of callee
|
|
// saved registers) after PEI.
|
|
if (PreRegAlloc && MI.isReturn())
|
|
return false;
|
|
|
|
// Avoid duplicating calls before register allocation. Calls presents a
|
|
// barrier to register allocation so duplicating them may end up increasing
|
|
// spills.
|
|
if (PreRegAlloc && MI.isCall())
|
|
return false;
|
|
|
|
// TailDuplicator::appendCopies will erroneously place COPYs after
|
|
// INLINEASM_BR instructions after 4b0aa5724fea, which demonstrates the same
|
|
// bug that was fixed in f7a53d82c090.
|
|
// FIXME: Use findPHICopyInsertPoint() to find the correct insertion point
|
|
// for the COPY when replacing PHIs.
|
|
if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
|
|
return false;
|
|
|
|
if (MI.isBundle())
|
|
InstrCount += MI.getBundleSize();
|
|
else if (!MI.isPHI() && !MI.isMetaInstruction())
|
|
InstrCount += 1;
|
|
|
|
if (InstrCount > MaxDuplicateCount)
|
|
return false;
|
|
}
|
|
|
|
// Check if any of the successors of TailBB has a PHI node in which the
|
|
// value corresponding to TailBB uses a subregister.
|
|
// If a phi node uses a register paired with a subregister, the actual
|
|
// "value type" of the phi may differ from the type of the register without
|
|
// any subregisters. Due to a bug, tail duplication may add a new operand
|
|
// without a necessary subregister, producing an invalid code. This is
|
|
// demonstrated by test/CodeGen/Hexagon/tail-dup-subreg-abort.ll.
|
|
// Disable tail duplication for this case for now, until the problem is
|
|
// fixed.
|
|
for (auto SB : TailBB.successors()) {
|
|
for (auto &I : *SB) {
|
|
if (!I.isPHI())
|
|
break;
|
|
unsigned Idx = getPHISrcRegOpIdx(&I, &TailBB);
|
|
assert(Idx != 0);
|
|
MachineOperand &PU = I.getOperand(Idx);
|
|
if (PU.getSubReg() != 0)
|
|
return false;
|
|
}
|
|
}
|
|
|
|
if (HasIndirectbr && PreRegAlloc)
|
|
return true;
|
|
|
|
if (IsSimple)
|
|
return true;
|
|
|
|
if (!PreRegAlloc)
|
|
return true;
|
|
|
|
return canCompletelyDuplicateBB(TailBB);
|
|
}
|
|
|
|
/// True if this BB has only one unconditional jump.
|
|
bool TailDuplicator::isSimpleBB(MachineBasicBlock *TailBB) {
|
|
if (TailBB->succ_size() != 1)
|
|
return false;
|
|
if (TailBB->pred_empty())
|
|
return false;
|
|
MachineBasicBlock::iterator I = TailBB->getFirstNonDebugInstr(true);
|
|
if (I == TailBB->end())
|
|
return true;
|
|
return I->isUnconditionalBranch();
|
|
}
|
|
|
|
static bool bothUsedInPHI(const MachineBasicBlock &A,
|
|
const SmallPtrSet<MachineBasicBlock *, 8> &SuccsB) {
|
|
for (MachineBasicBlock *BB : A.successors())
|
|
if (SuccsB.count(BB) && !BB->empty() && BB->begin()->isPHI())
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
bool TailDuplicator::canCompletelyDuplicateBB(MachineBasicBlock &BB) {
|
|
for (MachineBasicBlock *PredBB : BB.predecessors()) {
|
|
if (PredBB->succ_size() > 1)
|
|
return false;
|
|
|
|
MachineBasicBlock *PredTBB = nullptr, *PredFBB = nullptr;
|
|
SmallVector<MachineOperand, 4> PredCond;
|
|
if (TII->analyzeBranch(*PredBB, PredTBB, PredFBB, PredCond))
|
|
return false;
|
|
|
|
if (!PredCond.empty())
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool TailDuplicator::duplicateSimpleBB(
|
|
MachineBasicBlock *TailBB, SmallVectorImpl<MachineBasicBlock *> &TDBBs,
|
|
const DenseSet<Register> &UsedByPhi,
|
|
SmallVectorImpl<MachineInstr *> &Copies) {
|
|
SmallPtrSet<MachineBasicBlock *, 8> Succs(TailBB->succ_begin(),
|
|
TailBB->succ_end());
|
|
SmallVector<MachineBasicBlock *, 8> Preds(TailBB->predecessors());
|
|
bool Changed = false;
|
|
for (MachineBasicBlock *PredBB : Preds) {
|
|
if (PredBB->hasEHPadSuccessor() || PredBB->mayHaveInlineAsmBr())
|
|
continue;
|
|
|
|
if (bothUsedInPHI(*PredBB, Succs))
|
|
continue;
|
|
|
|
MachineBasicBlock *PredTBB = nullptr, *PredFBB = nullptr;
|
|
SmallVector<MachineOperand, 4> PredCond;
|
|
if (TII->analyzeBranch(*PredBB, PredTBB, PredFBB, PredCond))
|
|
continue;
|
|
|
|
Changed = true;
|
|
LLVM_DEBUG(dbgs() << "\nTail-duplicating into PredBB: " << *PredBB
|
|
<< "From simple Succ: " << *TailBB);
|
|
|
|
MachineBasicBlock *NewTarget = *TailBB->succ_begin();
|
|
MachineBasicBlock *NextBB = PredBB->getNextNode();
|
|
|
|
// Make PredFBB explicit.
|
|
if (PredCond.empty())
|
|
PredFBB = PredTBB;
|
|
|
|
// Make fall through explicit.
|
|
if (!PredTBB)
|
|
PredTBB = NextBB;
|
|
if (!PredFBB)
|
|
PredFBB = NextBB;
|
|
|
|
// Redirect
|
|
if (PredFBB == TailBB)
|
|
PredFBB = NewTarget;
|
|
if (PredTBB == TailBB)
|
|
PredTBB = NewTarget;
|
|
|
|
// Make the branch unconditional if possible
|
|
if (PredTBB == PredFBB) {
|
|
PredCond.clear();
|
|
PredFBB = nullptr;
|
|
}
|
|
|
|
// Avoid adding fall through branches.
|
|
if (PredFBB == NextBB)
|
|
PredFBB = nullptr;
|
|
if (PredTBB == NextBB && PredFBB == nullptr)
|
|
PredTBB = nullptr;
|
|
|
|
auto DL = PredBB->findBranchDebugLoc();
|
|
TII->removeBranch(*PredBB);
|
|
|
|
if (!PredBB->isSuccessor(NewTarget))
|
|
PredBB->replaceSuccessor(TailBB, NewTarget);
|
|
else {
|
|
PredBB->removeSuccessor(TailBB, true);
|
|
assert(PredBB->succ_size() <= 1);
|
|
}
|
|
|
|
if (PredTBB)
|
|
TII->insertBranch(*PredBB, PredTBB, PredFBB, PredCond, DL);
|
|
|
|
TDBBs.push_back(PredBB);
|
|
}
|
|
return Changed;
|
|
}
|
|
|
|
bool TailDuplicator::canTailDuplicate(MachineBasicBlock *TailBB,
|
|
MachineBasicBlock *PredBB) {
|
|
// EH edges are ignored by analyzeBranch.
|
|
if (PredBB->succ_size() > 1)
|
|
return false;
|
|
|
|
MachineBasicBlock *PredTBB = nullptr, *PredFBB = nullptr;
|
|
SmallVector<MachineOperand, 4> PredCond;
|
|
if (TII->analyzeBranch(*PredBB, PredTBB, PredFBB, PredCond))
|
|
return false;
|
|
if (!PredCond.empty())
|
|
return false;
|
|
return true;
|
|
}
|
|
|
|
/// If it is profitable, duplicate TailBB's contents in each
|
|
/// of its predecessors.
|
|
/// \p IsSimple result of isSimpleBB
|
|
/// \p TailBB Block to be duplicated.
|
|
/// \p ForcedLayoutPred When non-null, use this block as the layout predecessor
|
|
/// instead of the previous block in MF's order.
|
|
/// \p TDBBs A vector to keep track of all blocks tail-duplicated
|
|
/// into.
|
|
/// \p Copies A vector of copy instructions inserted. Used later to
|
|
/// walk all the inserted copies and remove redundant ones.
|
|
bool TailDuplicator::tailDuplicate(bool IsSimple, MachineBasicBlock *TailBB,
|
|
MachineBasicBlock *ForcedLayoutPred,
|
|
SmallVectorImpl<MachineBasicBlock *> &TDBBs,
|
|
SmallVectorImpl<MachineInstr *> &Copies,
|
|
SmallVectorImpl<MachineBasicBlock *> *CandidatePtr) {
|
|
LLVM_DEBUG(dbgs() << "\n*** Tail-duplicating " << printMBBReference(*TailBB)
|
|
<< '\n');
|
|
|
|
bool ShouldUpdateTerminators = TailBB->canFallThrough();
|
|
|
|
DenseSet<Register> UsedByPhi;
|
|
getRegsUsedByPHIs(*TailBB, &UsedByPhi);
|
|
|
|
if (IsSimple)
|
|
return duplicateSimpleBB(TailBB, TDBBs, UsedByPhi, Copies);
|
|
|
|
// Iterate through all the unique predecessors and tail-duplicate this
|
|
// block into them, if possible. Copying the list ahead of time also
|
|
// avoids trouble with the predecessor list reallocating.
|
|
bool Changed = false;
|
|
SmallSetVector<MachineBasicBlock *, 8> Preds;
|
|
if (CandidatePtr)
|
|
Preds.insert(CandidatePtr->begin(), CandidatePtr->end());
|
|
else
|
|
Preds.insert(TailBB->pred_begin(), TailBB->pred_end());
|
|
|
|
for (MachineBasicBlock *PredBB : Preds) {
|
|
assert(TailBB != PredBB &&
|
|
"Single-block loop should have been rejected earlier!");
|
|
|
|
if (!canTailDuplicate(TailBB, PredBB))
|
|
continue;
|
|
|
|
// Don't duplicate into a fall-through predecessor (at least for now).
|
|
// If profile is available, findDuplicateCandidates can choose better
|
|
// fall-through predecessor.
|
|
if (!(MF->getFunction().hasProfileData() && LayoutMode)) {
|
|
bool IsLayoutSuccessor = false;
|
|
if (ForcedLayoutPred)
|
|
IsLayoutSuccessor = (ForcedLayoutPred == PredBB);
|
|
else if (PredBB->isLayoutSuccessor(TailBB) && PredBB->canFallThrough())
|
|
IsLayoutSuccessor = true;
|
|
if (IsLayoutSuccessor)
|
|
continue;
|
|
}
|
|
|
|
LLVM_DEBUG(dbgs() << "\nTail-duplicating into PredBB: " << *PredBB
|
|
<< "From Succ: " << *TailBB);
|
|
|
|
TDBBs.push_back(PredBB);
|
|
|
|
// Remove PredBB's unconditional branch.
|
|
TII->removeBranch(*PredBB);
|
|
|
|
// Clone the contents of TailBB into PredBB.
|
|
DenseMap<Register, RegSubRegPair> LocalVRMap;
|
|
SmallVector<std::pair<Register, RegSubRegPair>, 4> CopyInfos;
|
|
for (MachineBasicBlock::iterator I = TailBB->begin(), E = TailBB->end();
|
|
I != E; /* empty */) {
|
|
MachineInstr *MI = &*I;
|
|
++I;
|
|
if (MI->isPHI()) {
|
|
// Replace the uses of the def of the PHI with the register coming
|
|
// from PredBB.
|
|
processPHI(MI, TailBB, PredBB, LocalVRMap, CopyInfos, UsedByPhi, true);
|
|
} else {
|
|
// Replace def of virtual registers with new registers, and update
|
|
// uses with PHI source register or the new registers.
|
|
duplicateInstruction(MI, TailBB, PredBB, LocalVRMap, UsedByPhi);
|
|
}
|
|
}
|
|
appendCopies(PredBB, CopyInfos, Copies);
|
|
|
|
NumTailDupAdded += TailBB->size() - 1; // subtract one for removed branch
|
|
|
|
// Update the CFG.
|
|
PredBB->removeSuccessor(PredBB->succ_begin());
|
|
assert(PredBB->succ_empty() &&
|
|
"TailDuplicate called on block with multiple successors!");
|
|
for (MachineBasicBlock *Succ : TailBB->successors())
|
|
PredBB->addSuccessor(Succ, MBPI->getEdgeProbability(TailBB, Succ));
|
|
|
|
// Update branches in pred to jump to tail's layout successor if needed.
|
|
if (ShouldUpdateTerminators)
|
|
PredBB->updateTerminator(TailBB->getNextNode());
|
|
|
|
Changed = true;
|
|
++NumTailDups;
|
|
}
|
|
|
|
// If TailBB was duplicated into all its predecessors except for the prior
|
|
// block, which falls through unconditionally, move the contents of this
|
|
// block into the prior block.
|
|
MachineBasicBlock *PrevBB = ForcedLayoutPred;
|
|
if (!PrevBB)
|
|
PrevBB = &*std::prev(TailBB->getIterator());
|
|
MachineBasicBlock *PriorTBB = nullptr, *PriorFBB = nullptr;
|
|
SmallVector<MachineOperand, 4> PriorCond;
|
|
// This has to check PrevBB->succ_size() because EH edges are ignored by
|
|
// analyzeBranch.
|
|
if (PrevBB->succ_size() == 1 &&
|
|
// Layout preds are not always CFG preds. Check.
|
|
*PrevBB->succ_begin() == TailBB &&
|
|
!TII->analyzeBranch(*PrevBB, PriorTBB, PriorFBB, PriorCond) &&
|
|
PriorCond.empty() &&
|
|
(!PriorTBB || PriorTBB == TailBB) &&
|
|
TailBB->pred_size() == 1 &&
|
|
!TailBB->hasAddressTaken()) {
|
|
LLVM_DEBUG(dbgs() << "\nMerging into block: " << *PrevBB
|
|
<< "From MBB: " << *TailBB);
|
|
// There may be a branch to the layout successor. This is unlikely but it
|
|
// happens. The correct thing to do is to remove the branch before
|
|
// duplicating the instructions in all cases.
|
|
TII->removeBranch(*PrevBB);
|
|
if (PreRegAlloc) {
|
|
DenseMap<Register, RegSubRegPair> LocalVRMap;
|
|
SmallVector<std::pair<Register, RegSubRegPair>, 4> CopyInfos;
|
|
MachineBasicBlock::iterator I = TailBB->begin();
|
|
// Process PHI instructions first.
|
|
while (I != TailBB->end() && I->isPHI()) {
|
|
// Replace the uses of the def of the PHI with the register coming
|
|
// from PredBB.
|
|
MachineInstr *MI = &*I++;
|
|
processPHI(MI, TailBB, PrevBB, LocalVRMap, CopyInfos, UsedByPhi, true);
|
|
}
|
|
|
|
// Now copy the non-PHI instructions.
|
|
while (I != TailBB->end()) {
|
|
// Replace def of virtual registers with new registers, and update
|
|
// uses with PHI source register or the new registers.
|
|
MachineInstr *MI = &*I++;
|
|
assert(!MI->isBundle() && "Not expecting bundles before regalloc!");
|
|
duplicateInstruction(MI, TailBB, PrevBB, LocalVRMap, UsedByPhi);
|
|
MI->eraseFromParent();
|
|
}
|
|
appendCopies(PrevBB, CopyInfos, Copies);
|
|
} else {
|
|
TII->removeBranch(*PrevBB);
|
|
// No PHIs to worry about, just splice the instructions over.
|
|
PrevBB->splice(PrevBB->end(), TailBB, TailBB->begin(), TailBB->end());
|
|
}
|
|
PrevBB->removeSuccessor(PrevBB->succ_begin());
|
|
assert(PrevBB->succ_empty());
|
|
PrevBB->transferSuccessors(TailBB);
|
|
|
|
// Update branches in PrevBB based on Tail's layout successor.
|
|
if (ShouldUpdateTerminators)
|
|
PrevBB->updateTerminator(TailBB->getNextNode());
|
|
|
|
TDBBs.push_back(PrevBB);
|
|
Changed = true;
|
|
}
|
|
|
|
// If this is after register allocation, there are no phis to fix.
|
|
if (!PreRegAlloc)
|
|
return Changed;
|
|
|
|
// If we made no changes so far, we are safe.
|
|
if (!Changed)
|
|
return Changed;
|
|
|
|
// Handle the nasty case in that we duplicated a block that is part of a loop
|
|
// into some but not all of its predecessors. For example:
|
|
// 1 -> 2 <-> 3 |
|
|
// \ |
|
|
// \---> rest |
|
|
// if we duplicate 2 into 1 but not into 3, we end up with
|
|
// 12 -> 3 <-> 2 -> rest |
|
|
// \ / |
|
|
// \----->-----/ |
|
|
// If there was a "var = phi(1, 3)" in 2, it has to be ultimately replaced
|
|
// with a phi in 3 (which now dominates 2).
|
|
// What we do here is introduce a copy in 3 of the register defined by the
|
|
// phi, just like when we are duplicating 2 into 3, but we don't copy any
|
|
// real instructions or remove the 3 -> 2 edge from the phi in 2.
|
|
for (MachineBasicBlock *PredBB : Preds) {
|
|
if (is_contained(TDBBs, PredBB))
|
|
continue;
|
|
|
|
// EH edges
|
|
if (PredBB->succ_size() != 1)
|
|
continue;
|
|
|
|
DenseMap<Register, RegSubRegPair> LocalVRMap;
|
|
SmallVector<std::pair<Register, RegSubRegPair>, 4> CopyInfos;
|
|
MachineBasicBlock::iterator I = TailBB->begin();
|
|
// Process PHI instructions first.
|
|
while (I != TailBB->end() && I->isPHI()) {
|
|
// Replace the uses of the def of the PHI with the register coming
|
|
// from PredBB.
|
|
MachineInstr *MI = &*I++;
|
|
processPHI(MI, TailBB, PredBB, LocalVRMap, CopyInfos, UsedByPhi, false);
|
|
}
|
|
appendCopies(PredBB, CopyInfos, Copies);
|
|
}
|
|
|
|
return Changed;
|
|
}
|
|
|
|
/// At the end of the block \p MBB generate COPY instructions between registers
|
|
/// described by \p CopyInfos. Append resulting instructions to \p Copies.
|
|
void TailDuplicator::appendCopies(MachineBasicBlock *MBB,
|
|
SmallVectorImpl<std::pair<Register, RegSubRegPair>> &CopyInfos,
|
|
SmallVectorImpl<MachineInstr*> &Copies) {
|
|
MachineBasicBlock::iterator Loc = MBB->getFirstTerminator();
|
|
const MCInstrDesc &CopyD = TII->get(TargetOpcode::COPY);
|
|
for (auto &CI : CopyInfos) {
|
|
auto C = BuildMI(*MBB, Loc, DebugLoc(), CopyD, CI.first)
|
|
.addReg(CI.second.Reg, 0, CI.second.SubReg);
|
|
Copies.push_back(C);
|
|
}
|
|
}
|
|
|
|
/// Remove the specified dead machine basic block from the function, updating
|
|
/// the CFG.
|
|
void TailDuplicator::removeDeadBlock(
|
|
MachineBasicBlock *MBB,
|
|
function_ref<void(MachineBasicBlock *)> *RemovalCallback) {
|
|
assert(MBB->pred_empty() && "MBB must be dead!");
|
|
LLVM_DEBUG(dbgs() << "\nRemoving MBB: " << *MBB);
|
|
|
|
MachineFunction *MF = MBB->getParent();
|
|
// Update the call site info.
|
|
for (const MachineInstr &MI : *MBB)
|
|
if (MI.shouldUpdateCallSiteInfo())
|
|
MF->eraseCallSiteInfo(&MI);
|
|
|
|
if (RemovalCallback)
|
|
(*RemovalCallback)(MBB);
|
|
|
|
// Remove all successors.
|
|
while (!MBB->succ_empty())
|
|
MBB->removeSuccessor(MBB->succ_end() - 1);
|
|
|
|
// Remove the block.
|
|
MBB->eraseFromParent();
|
|
}
|