llvm-project/llvm
David Green e9adcbde31 [AArch64] Model Cortex-A55 Q register NEON instructions
Cortex-A55 has 2 64bit NEON vector units, meaning a 128bit instruction
requires taking both units (and can only be issued as the first
instruction in a dual issue pair). This patch models that by splitting
the WriteV SchedWrite into two - the WriteVd that reads/writes only
64bit operands, and the WriteVq that read/writes 128bit registers. The
A55 schedule then uses this distinction to model the WriteVq as taking
both resource units, and starting a Schedule Group and WriteVd as taking
one as before.

I believe this is more correct, even if it does not lead to much better
performance.

Differential Revision: https://reviews.llvm.org/D108766
2021-09-29 16:55:31 +01:00
..
benchmarks
bindings [NFC][C API] Make LLVMSetInstrParamAlignment's index param type LLVMAttributeIndex 2021-09-07 15:13:45 -07:00
cmake [CMake] Add detection for the mold linker in AddLLVM.cmake. 2021-09-28 17:46:52 +05:30
docs [VP] Vector predicated vector splice intrinsic 2021-09-29 10:43:36 +02:00
examples [ORC][examples] Port LLJITWithRemoteDebugging to SimpleRemoteEPC 2021-09-29 10:20:41 +02:00
include [TTI] BasicTTI::getInterleavedMemoryOpCost(): use getScalarizationOverhead() 2021-09-29 16:41:53 +01:00
lib [AArch64] Model Cortex-A55 Q register NEON instructions 2021-09-29 16:55:31 +01:00
projects
resources
runtimes
test [AArch64] Model Cortex-A55 Q register NEON instructions 2021-09-29 16:55:31 +01:00
tools [LTO][Legacy] Add -debug-pass-manager option to enable pass run/skip trace. 2021-09-29 12:17:53 +00:00
unittests [VP] Vector predicated vector splice intrinsic 2021-09-29 10:43:36 +02:00
utils [gn build] Port c07f709969 2021-09-29 01:03:11 +00:00
.clang-format
.clang-tidy
.gitattributes
.gitignore
CMakeLists.txt Revert "[CMake] Enable LLVM_ENABLE_PER_TARGET_RUNTIME_DIR by default on Linux" 2021-09-28 18:23:43 +03:00
CODE_OWNERS.TXT
CREDITS.TXT
LICENSE.TXT
README.txt
RELEASE_TESTERS.TXT
configure
llvm.spec.in

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