forked from OSchip/llvm-project
629 lines
24 KiB
LLVM
629 lines
24 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -aa-pipeline=basic-aa -passes='loop-mssa(licm)' -S | FileCheck %s
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@X = global i32 0 ; <i32*> [#uses=1]
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declare void @foo()
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declare i32 @llvm.bitreverse.i32(i32)
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; This testcase tests for a problem where LICM hoists
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; potentially trapping instructions when they are not guaranteed to execute.
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define i32 @test1(i1 %c) {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: [[A:%.*]] = load i32, i32* @X, align 4
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: Loop:
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; CHECK-NEXT: call void @foo()
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; CHECK-NEXT: br i1 [[C:%.*]], label [[LOOPTAIL:%.*]], label [[IFUNEQUAL:%.*]]
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; CHECK: IfUnEqual:
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; CHECK-NEXT: [[B1:%.*]] = sdiv i32 4, [[A]]
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; CHECK-NEXT: br label [[LOOPTAIL]]
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; CHECK: LoopTail:
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; CHECK-NEXT: [[B:%.*]] = phi i32 [ 0, [[LOOP]] ], [ [[B1]], [[IFUNEQUAL]] ]
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; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[OUT:%.*]]
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; CHECK: Out:
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; CHECK-NEXT: [[B_LCSSA:%.*]] = phi i32 [ [[B]], [[LOOPTAIL]] ]
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; CHECK-NEXT: [[C:%.*]] = sub i32 [[A]], [[B_LCSSA]]
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; CHECK-NEXT: ret i32 [[C]]
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;
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%A = load i32, i32* @X ; <i32> [#uses=2]
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br label %Loop
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Loop: ; preds = %LoopTail, %0
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call void @foo( )
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br i1 %c, label %LoopTail, label %IfUnEqual
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IfUnEqual: ; preds = %Loop
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%B1 = sdiv i32 4, %A ; <i32> [#uses=1]
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br label %LoopTail
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LoopTail: ; preds = %IfUnEqual, %Loop
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%B = phi i32 [ 0, %Loop ], [ %B1, %IfUnEqual ] ; <i32> [#uses=1]
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br i1 %c, label %Loop, label %Out
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Out: ; preds = %LoopTail
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%C = sub i32 %A, %B ; <i32> [#uses=1]
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ret i32 %C
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}
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declare void @foo2(i32) nounwind
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;; It is ok and desirable to hoist this potentially trapping instruction.
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define i32 @test2(i1 %c) {
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: [[A:%.*]] = load i32, i32* @X, align 4
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; CHECK-NEXT: [[B:%.*]] = sdiv i32 4, [[A]]
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: Loop:
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; CHECK-NEXT: br label [[LOOP2:%.*]]
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; CHECK: loop2:
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; CHECK-NEXT: call void @foo2(i32 [[B]])
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; CHECK-NEXT: br i1 [[C:%.*]], label [[LOOP]], label [[OUT:%.*]]
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; CHECK: Out:
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; CHECK-NEXT: [[B_LCSSA:%.*]] = phi i32 [ [[B]], [[LOOP2]] ]
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; CHECK-NEXT: [[C:%.*]] = sub i32 [[A]], [[B_LCSSA]]
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; CHECK-NEXT: ret i32 [[C]]
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;
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%A = load i32, i32* @X
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br label %Loop
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Loop:
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;; Should have hoisted this div!
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%B = sdiv i32 4, %A
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br label %loop2
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loop2:
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call void @foo2( i32 %B )
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br i1 %c, label %Loop, label %Out
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Out:
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%C = sub i32 %A, %B
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ret i32 %C
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}
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; This loop invariant instruction should be constant folded, not hoisted.
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define i32 @test3(i1 %c) {
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; CHECK-LABEL: @test3(
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; CHECK-NEXT: [[A:%.*]] = load i32, i32* @X, align 4
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: Loop:
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; CHECK-NEXT: call void @foo2(i32 6)
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; CHECK-NEXT: br i1 [[C:%.*]], label [[LOOP]], label [[OUT:%.*]]
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; CHECK: Out:
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; CHECK-NEXT: [[B_LCSSA:%.*]] = phi i32 [ 6, [[LOOP]] ]
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; CHECK-NEXT: [[C:%.*]] = sub i32 [[A]], [[B_LCSSA]]
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; CHECK-NEXT: ret i32 [[C]]
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;
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%A = load i32, i32* @X ; <i32> [#uses=2]
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br label %Loop
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Loop:
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%B = add i32 4, 2 ; <i32> [#uses=2]
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call void @foo2( i32 %B )
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br i1 %c, label %Loop, label %Out
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Out: ; preds = %Loop
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%C = sub i32 %A, %B ; <i32> [#uses=1]
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ret i32 %C
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}
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define i32 @test4(i32 %x, i32 %y) nounwind uwtable ssp {
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; CHECK-LABEL: @test4(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[I_02:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[N_01:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[ADD:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: call void @foo_may_call_exit(i32 0)
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; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[ADD]] = add nsw i32 [[N_01]], [[DIV]]
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; CHECK-NEXT: [[INC]] = add nsw i32 [[I_02]], 1
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[INC]], 10000
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; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END:%.*]]
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; CHECK: for.end:
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; CHECK-NEXT: [[N_0_LCSSA:%.*]] = phi i32 [ [[ADD]], [[FOR_BODY]] ]
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; CHECK-NEXT: ret i32 [[N_0_LCSSA]]
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;
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%i.02 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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%n.01 = phi i32 [ 0, %entry ], [ %add, %for.body ]
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call void @foo_may_call_exit(i32 0)
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%div = sdiv i32 %x, %y
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%add = add nsw i32 %n.01, %div
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%inc = add nsw i32 %i.02, 1
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%cmp = icmp slt i32 %inc, 10000
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br i1 %cmp, label %for.body, label %for.end
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for.end: ; preds = %for.body
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%n.0.lcssa = phi i32 [ %add, %for.body ]
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ret i32 %n.0.lcssa
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}
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declare void @foo_may_call_exit(i32)
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; PR14854
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define { i32*, i32 } @test5(i32 %i, { i32*, i32 } %e) {
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; CHECK-LABEL: @test5(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[OUT:%.*]] = extractvalue { i32*, i32 } [[E:%.*]], 1
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; CHECK-NEXT: br label [[TAILRECURSE:%.*]]
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; CHECK: tailrecurse:
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; CHECK-NEXT: [[I_TR:%.*]] = phi i32 [ [[I:%.*]], [[ENTRY:%.*]] ], [ [[CMP2:%.*]], [[THEN:%.*]] ]
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; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[OUT]], [[I_TR]]
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; CHECK-NEXT: br i1 [[CMP1]], label [[THEN]], label [[IFEND:%.*]]
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; CHECK: then:
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; CHECK-NEXT: call void @foo()
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; CHECK-NEXT: [[CMP2]] = add i32 [[I_TR]], 1
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; CHECK-NEXT: br label [[TAILRECURSE]]
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; CHECK: ifend:
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; CHECK-NEXT: [[D_LE:%.*]] = insertvalue { i32*, i32 } [[E]], i32* null, 0
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; CHECK-NEXT: ret { i32*, i32 } [[D_LE]]
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;
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entry:
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br label %tailrecurse
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tailrecurse: ; preds = %then, %entry
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%i.tr = phi i32 [ %i, %entry ], [ %cmp2, %then ]
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%out = extractvalue { i32*, i32 } %e, 1
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%d = insertvalue { i32*, i32 } %e, i32* null, 0
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%cmp1 = icmp sgt i32 %out, %i.tr
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br i1 %cmp1, label %then, label %ifend
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then: ; preds = %tailrecurse
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call void @foo()
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%cmp2 = add i32 %i.tr, 1
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br label %tailrecurse
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ifend: ; preds = %tailrecurse
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ret { i32*, i32 } %d
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}
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define void @test6(float %f) #2 {
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; CHECK-LABEL: @test6(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[NEG:%.*]] = fneg float [[F:%.*]]
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: call void @foo_may_call_exit(i32 0)
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; CHECK-NEXT: call void @use(float [[NEG]])
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; CHECK-NEXT: [[INC]] = add nsw i32 [[I]], 1
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[INC]], 10000
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; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END:%.*]]
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; CHECK: for.end:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%i = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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call void @foo_may_call_exit(i32 0)
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%neg = fneg float %f
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call void @use(float %neg)
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%inc = add nsw i32 %i, 1
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%cmp = icmp slt i32 %inc, 10000
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br i1 %cmp, label %for.body, label %for.end
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for.end: ; preds = %for.body
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ret void
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}
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declare void @use(float)
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define i32 @hoist_bitreverse(i32 %0) {
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; CHECK-LABEL: @hoist_bitreverse(
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; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.bitreverse.i32(i32 [[TMP0:%.*]])
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; CHECK-NEXT: br label [[HEADER:%.*]]
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; CHECK: header:
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; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ 0, [[TMP1:%.*]] ], [ [[TMP5:%.*]], [[LATCH:%.*]] ]
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; CHECK-NEXT: [[TMP3:%.*]] = phi i32 [ 0, [[TMP1]] ], [ [[TMP6:%.*]], [[LATCH]] ]
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; CHECK-NEXT: [[TMP4:%.*]] = icmp slt i32 [[TMP3]], 1024
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; CHECK-NEXT: br i1 [[TMP4]], label [[BODY:%.*]], label [[RETURN:%.*]]
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; CHECK: body:
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; CHECK-NEXT: [[TMP5]] = add i32 [[SUM]], [[TMP2]]
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; CHECK-NEXT: br label [[LATCH]]
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; CHECK: latch:
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; CHECK-NEXT: [[TMP6]] = add nsw i32 [[TMP3]], 1
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; CHECK-NEXT: br label [[HEADER]]
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; CHECK: return:
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; CHECK-NEXT: [[SUM_LCSSA:%.*]] = phi i32 [ [[SUM]], [[HEADER]] ]
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; CHECK-NEXT: ret i32 [[SUM_LCSSA]]
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;
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br label %header
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header:
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%sum = phi i32 [ 0, %1 ], [ %5, %latch ]
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%2 = phi i32 [ 0, %1 ], [ %6, %latch ]
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%3 = icmp slt i32 %2, 1024
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br i1 %3, label %body, label %return
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body:
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%4 = call i32 @llvm.bitreverse.i32(i32 %0)
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%5 = add i32 %sum, %4
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br label %latch
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latch:
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%6 = add nsw i32 %2, 1
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br label %header
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return:
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ret i32 %sum
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}
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; Can neither sink nor hoist
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define i32 @test_volatile(i1 %c) {
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; CHECK-LABEL: @test_volatile(
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: Loop:
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; CHECK-NEXT: [[A:%.*]] = load volatile i32, i32* @X, align 4
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; CHECK-NEXT: br i1 [[C:%.*]], label [[LOOP]], label [[OUT:%.*]]
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; CHECK: Out:
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; CHECK-NEXT: [[A_LCSSA:%.*]] = phi i32 [ [[A]], [[LOOP]] ]
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; CHECK-NEXT: ret i32 [[A_LCSSA]]
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;
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br label %Loop
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Loop:
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%A = load volatile i32, i32* @X
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br i1 %c, label %Loop, label %Out
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Out:
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ret i32 %A
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}
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declare {}* @llvm.invariant.start.p0i8(i64, i8* nocapture) nounwind readonly
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declare void @llvm.invariant.end.p0i8({}*, i64, i8* nocapture) nounwind
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declare void @escaping.invariant.start({}*) nounwind
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; invariant.start dominates the load, and in this scope, the
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; load is invariant. So, we can hoist the `addrld` load out of the loop.
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define i32 @test_fence(i8* %addr, i32 %n, i8* %volatile) {
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; CHECK-LABEL: @test_fence(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, i8* [[ADDR:%.*]], i64 8
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; CHECK-NEXT: [[ADDR_I:%.*]] = bitcast i8* [[GEP]] to i32*
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; CHECK-NEXT: store atomic i32 5, i32* [[ADDR_I]] unordered, align 8
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; CHECK-NEXT: fence release
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; CHECK-NEXT: [[INVST:%.*]] = call {}* @llvm.invariant.start.p0i8(i64 4, i8* [[GEP]])
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; CHECK-NEXT: [[ADDRLD:%.*]] = load atomic i32, i32* [[ADDR_I]] unordered, align 8
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[SUM_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY]] ]
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; CHECK-NEXT: [[VOLLOAD:%.*]] = load atomic i8, i8* [[VOLATILE:%.*]] unordered, align 8
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; CHECK-NEXT: fence acquire
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; CHECK-NEXT: [[VOLCHK:%.*]] = icmp eq i8 [[VOLLOAD]], 0
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; CHECK-NEXT: [[SEL:%.*]] = select i1 [[VOLCHK]], i32 0, i32 [[ADDRLD]]
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; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SEL]], [[SUM]]
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; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1
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; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[INDVAR_NEXT]], [[N:%.*]]
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; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[LOOPEXIT:%.*]]
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; CHECK: loopexit:
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; CHECK-NEXT: [[SUM_LCSSA:%.*]] = phi i32 [ [[SUM]], [[LOOP]] ]
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; CHECK-NEXT: ret i32 [[SUM_LCSSA]]
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;
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entry:
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%gep = getelementptr inbounds i8, i8* %addr, i64 8
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%addr.i = bitcast i8* %gep to i32 *
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store atomic i32 5, i32 * %addr.i unordered, align 8
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fence release
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%invst = call {}* @llvm.invariant.start.p0i8(i64 4, i8* %gep)
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br label %loop
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loop:
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%indvar = phi i32 [ %indvar.next, %loop ], [ 0, %entry ]
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%sum = phi i32 [ %sum.next, %loop ], [ 0, %entry ]
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%volload = load atomic i8, i8* %volatile unordered, align 8
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fence acquire
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%volchk = icmp eq i8 %volload, 0
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%addrld = load atomic i32, i32* %addr.i unordered, align 8
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%sel = select i1 %volchk, i32 0, i32 %addrld
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%sum.next = add i32 %sel, %sum
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%indvar.next = add i32 %indvar, 1
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%cond = icmp slt i32 %indvar.next, %n
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br i1 %cond, label %loop, label %loopexit
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loopexit:
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ret i32 %sum
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}
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; Same as test above, but the load is no longer invariant (presence of
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; invariant.end). We cannot hoist the addrld out of loop.
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define i32 @test_fence1(i8* %addr, i32 %n, i8* %volatile) {
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; CHECK-LABEL: @test_fence1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, i8* [[ADDR:%.*]], i64 8
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; CHECK-NEXT: [[ADDR_I:%.*]] = bitcast i8* [[GEP]] to i32*
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; CHECK-NEXT: store atomic i32 5, i32* [[ADDR_I]] unordered, align 8
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; CHECK-NEXT: fence release
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; CHECK-NEXT: [[INVST:%.*]] = call {}* @llvm.invariant.start.p0i8(i64 4, i8* [[GEP]])
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; CHECK-NEXT: call void @llvm.invariant.end.p0i8({}* [[INVST]], i64 4, i8* [[GEP]])
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[SUM_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY]] ]
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; CHECK-NEXT: [[VOLLOAD:%.*]] = load atomic i8, i8* [[VOLATILE:%.*]] unordered, align 8
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; CHECK-NEXT: fence acquire
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; CHECK-NEXT: [[VOLCHK:%.*]] = icmp eq i8 [[VOLLOAD]], 0
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; CHECK-NEXT: [[ADDRLD:%.*]] = load atomic i32, i32* [[ADDR_I]] unordered, align 8
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; CHECK-NEXT: [[SEL:%.*]] = select i1 [[VOLCHK]], i32 0, i32 [[ADDRLD]]
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; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SEL]], [[SUM]]
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; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1
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; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[INDVAR_NEXT]], [[N:%.*]]
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; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[LOOPEXIT:%.*]]
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; CHECK: loopexit:
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; CHECK-NEXT: [[SUM_LCSSA:%.*]] = phi i32 [ [[SUM]], [[LOOP]] ]
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; CHECK-NEXT: ret i32 [[SUM_LCSSA]]
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;
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entry:
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%gep = getelementptr inbounds i8, i8* %addr, i64 8
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%addr.i = bitcast i8* %gep to i32 *
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store atomic i32 5, i32 * %addr.i unordered, align 8
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fence release
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%invst = call {}* @llvm.invariant.start.p0i8(i64 4, i8* %gep)
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call void @llvm.invariant.end.p0i8({}* %invst, i64 4, i8* %gep)
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br label %loop
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loop:
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%indvar = phi i32 [ %indvar.next, %loop ], [ 0, %entry ]
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%sum = phi i32 [ %sum.next, %loop ], [ 0, %entry ]
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%volload = load atomic i8, i8* %volatile unordered, align 8
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fence acquire
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%volchk = icmp eq i8 %volload, 0
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%addrld = load atomic i32, i32* %addr.i unordered, align 8
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%sel = select i1 %volchk, i32 0, i32 %addrld
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%sum.next = add i32 %sel, %sum
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%indvar.next = add i32 %indvar, 1
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%cond = icmp slt i32 %indvar.next, %n
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br i1 %cond, label %loop, label %loopexit
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loopexit:
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ret i32 %sum
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}
|
|
|
|
; same as test above, but instead of invariant.end, we have the result of
|
|
; invariant.start escaping through a call. We cannot hoist the load.
|
|
define i32 @test_fence2(i8* %addr, i32 %n, i8* %volatile) {
|
|
; CHECK-LABEL: @test_fence2(
|
|
; CHECK-NEXT: entry:
|
|
; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, i8* [[ADDR:%.*]], i64 8
|
|
; CHECK-NEXT: [[ADDR_I:%.*]] = bitcast i8* [[GEP]] to i32*
|
|
; CHECK-NEXT: store atomic i32 5, i32* [[ADDR_I]] unordered, align 8
|
|
; CHECK-NEXT: fence release
|
|
; CHECK-NEXT: [[INVST:%.*]] = call {}* @llvm.invariant.start.p0i8(i64 4, i8* [[GEP]])
|
|
; CHECK-NEXT: call void @escaping.invariant.start({}* [[INVST]])
|
|
; CHECK-NEXT: br label [[LOOP:%.*]]
|
|
; CHECK: loop:
|
|
; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
|
|
; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[SUM_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY]] ]
|
|
; CHECK-NEXT: [[VOLLOAD:%.*]] = load atomic i8, i8* [[VOLATILE:%.*]] unordered, align 8
|
|
; CHECK-NEXT: fence acquire
|
|
; CHECK-NEXT: [[VOLCHK:%.*]] = icmp eq i8 [[VOLLOAD]], 0
|
|
; CHECK-NEXT: [[ADDRLD:%.*]] = load atomic i32, i32* [[ADDR_I]] unordered, align 8
|
|
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[VOLCHK]], i32 0, i32 [[ADDRLD]]
|
|
; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SEL]], [[SUM]]
|
|
; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1
|
|
; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[INDVAR_NEXT]], [[N:%.*]]
|
|
; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[LOOPEXIT:%.*]]
|
|
; CHECK: loopexit:
|
|
; CHECK-NEXT: [[SUM_LCSSA:%.*]] = phi i32 [ [[SUM]], [[LOOP]] ]
|
|
; CHECK-NEXT: ret i32 [[SUM_LCSSA]]
|
|
;
|
|
entry:
|
|
%gep = getelementptr inbounds i8, i8* %addr, i64 8
|
|
%addr.i = bitcast i8* %gep to i32 *
|
|
store atomic i32 5, i32 * %addr.i unordered, align 8
|
|
fence release
|
|
%invst = call {}* @llvm.invariant.start.p0i8(i64 4, i8* %gep)
|
|
call void @escaping.invariant.start({}* %invst)
|
|
br label %loop
|
|
|
|
loop:
|
|
%indvar = phi i32 [ %indvar.next, %loop ], [ 0, %entry ]
|
|
%sum = phi i32 [ %sum.next, %loop ], [ 0, %entry ]
|
|
%volload = load atomic i8, i8* %volatile unordered, align 8
|
|
fence acquire
|
|
%volchk = icmp eq i8 %volload, 0
|
|
%addrld = load atomic i32, i32* %addr.i unordered, align 8
|
|
%sel = select i1 %volchk, i32 0, i32 %addrld
|
|
%sum.next = add i32 %sel, %sum
|
|
%indvar.next = add i32 %indvar, 1
|
|
%cond = icmp slt i32 %indvar.next, %n
|
|
br i1 %cond, label %loop, label %loopexit
|
|
|
|
loopexit:
|
|
ret i32 %sum
|
|
}
|
|
|
|
; FIXME: invariant.start dominates the load, and in this scope, the
|
|
; load is invariant. So, we can hoist the `addrld` load out of the loop.
|
|
; Consider the loadoperand addr.i bitcasted before being passed to
|
|
; invariant.start
|
|
define i32 @test_fence3(i32* %addr, i32 %n, i8* %volatile) {
|
|
; CHECK-LABEL: @test_fence3(
|
|
; CHECK-NEXT: entry:
|
|
; CHECK-NEXT: [[ADDR_I:%.*]] = getelementptr inbounds i32, i32* [[ADDR:%.*]], i64 8
|
|
; CHECK-NEXT: [[GEP:%.*]] = bitcast i32* [[ADDR_I]] to i8*
|
|
; CHECK-NEXT: store atomic i32 5, i32* [[ADDR_I]] unordered, align 8
|
|
; CHECK-NEXT: fence release
|
|
; CHECK-NEXT: [[INVST:%.*]] = call {}* @llvm.invariant.start.p0i8(i64 4, i8* [[GEP]])
|
|
; CHECK-NEXT: br label [[LOOP:%.*]]
|
|
; CHECK: loop:
|
|
; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
|
|
; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[SUM_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY]] ]
|
|
; CHECK-NEXT: [[VOLLOAD:%.*]] = load atomic i8, i8* [[VOLATILE:%.*]] unordered, align 8
|
|
; CHECK-NEXT: fence acquire
|
|
; CHECK-NEXT: [[VOLCHK:%.*]] = icmp eq i8 [[VOLLOAD]], 0
|
|
; CHECK-NEXT: [[ADDRLD:%.*]] = load atomic i32, i32* [[ADDR_I]] unordered, align 8
|
|
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[VOLCHK]], i32 0, i32 [[ADDRLD]]
|
|
; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SEL]], [[SUM]]
|
|
; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1
|
|
; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[INDVAR_NEXT]], [[N:%.*]]
|
|
; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[LOOPEXIT:%.*]]
|
|
; CHECK: loopexit:
|
|
; CHECK-NEXT: [[SUM_LCSSA:%.*]] = phi i32 [ [[SUM]], [[LOOP]] ]
|
|
; CHECK-NEXT: ret i32 [[SUM_LCSSA]]
|
|
;
|
|
entry:
|
|
%addr.i = getelementptr inbounds i32, i32* %addr, i64 8
|
|
%gep = bitcast i32* %addr.i to i8 *
|
|
store atomic i32 5, i32 * %addr.i unordered, align 8
|
|
fence release
|
|
%invst = call {}* @llvm.invariant.start.p0i8(i64 4, i8* %gep)
|
|
br label %loop
|
|
|
|
loop:
|
|
%indvar = phi i32 [ %indvar.next, %loop ], [ 0, %entry ]
|
|
%sum = phi i32 [ %sum.next, %loop ], [ 0, %entry ]
|
|
%volload = load atomic i8, i8* %volatile unordered, align 8
|
|
fence acquire
|
|
%volchk = icmp eq i8 %volload, 0
|
|
%addrld = load atomic i32, i32* %addr.i unordered, align 8
|
|
%sel = select i1 %volchk, i32 0, i32 %addrld
|
|
%sum.next = add i32 %sel, %sum
|
|
%indvar.next = add i32 %indvar, 1
|
|
%cond = icmp slt i32 %indvar.next, %n
|
|
br i1 %cond, label %loop, label %loopexit
|
|
|
|
loopexit:
|
|
ret i32 %sum
|
|
}
|
|
|
|
; We should not hoist the addrld out of the loop.
|
|
define i32 @test_fence4(i32* %addr, i32 %n, i8* %volatile) {
|
|
; CHECK-LABEL: @test_fence4(
|
|
; CHECK-NEXT: entry:
|
|
; CHECK-NEXT: [[ADDR_I:%.*]] = getelementptr inbounds i32, i32* [[ADDR:%.*]], i64 8
|
|
; CHECK-NEXT: [[GEP:%.*]] = bitcast i32* [[ADDR_I]] to i8*
|
|
; CHECK-NEXT: br label [[LOOP:%.*]]
|
|
; CHECK: loop:
|
|
; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
|
|
; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[SUM_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY]] ]
|
|
; CHECK-NEXT: store atomic i32 5, i32* [[ADDR_I]] unordered, align 8
|
|
; CHECK-NEXT: fence release
|
|
; CHECK-NEXT: [[INVST:%.*]] = call {}* @llvm.invariant.start.p0i8(i64 4, i8* [[GEP]])
|
|
; CHECK-NEXT: [[VOLLOAD:%.*]] = load atomic i8, i8* [[VOLATILE:%.*]] unordered, align 8
|
|
; CHECK-NEXT: fence acquire
|
|
; CHECK-NEXT: [[VOLCHK:%.*]] = icmp eq i8 [[VOLLOAD]], 0
|
|
; CHECK-NEXT: [[ADDRLD:%.*]] = load atomic i32, i32* [[ADDR_I]] unordered, align 8
|
|
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[VOLCHK]], i32 0, i32 [[ADDRLD]]
|
|
; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SEL]], [[SUM]]
|
|
; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1
|
|
; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[INDVAR_NEXT]], [[N:%.*]]
|
|
; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[LOOPEXIT:%.*]]
|
|
; CHECK: loopexit:
|
|
; CHECK-NEXT: [[SUM_LCSSA:%.*]] = phi i32 [ [[SUM]], [[LOOP]] ]
|
|
; CHECK-NEXT: ret i32 [[SUM_LCSSA]]
|
|
;
|
|
entry:
|
|
%addr.i = getelementptr inbounds i32, i32* %addr, i64 8
|
|
%gep = bitcast i32* %addr.i to i8 *
|
|
br label %loop
|
|
|
|
loop:
|
|
%indvar = phi i32 [ %indvar.next, %loop ], [ 0, %entry ]
|
|
%sum = phi i32 [ %sum.next, %loop ], [ 0, %entry ]
|
|
store atomic i32 5, i32 * %addr.i unordered, align 8
|
|
fence release
|
|
%invst = call {}* @llvm.invariant.start.p0i8(i64 4, i8* %gep)
|
|
%volload = load atomic i8, i8* %volatile unordered, align 8
|
|
fence acquire
|
|
%volchk = icmp eq i8 %volload, 0
|
|
%addrld = load atomic i32, i32* %addr.i unordered, align 8
|
|
%sel = select i1 %volchk, i32 0, i32 %addrld
|
|
%sum.next = add i32 %sel, %sum
|
|
%indvar.next = add i32 %indvar, 1
|
|
%cond = icmp slt i32 %indvar.next, %n
|
|
br i1 %cond, label %loop, label %loopexit
|
|
|
|
loopexit:
|
|
ret i32 %sum
|
|
}
|
|
|
|
; We can't hoist the invariant load out of the loop because
|
|
; the marker is given a variable size (-1).
|
|
define i32 @test_fence5(i8* %addr, i32 %n, i8* %volatile) {
|
|
; CHECK-LABEL: @test_fence5(
|
|
; CHECK-NEXT: entry:
|
|
; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, i8* [[ADDR:%.*]], i64 8
|
|
; CHECK-NEXT: [[ADDR_I:%.*]] = bitcast i8* [[GEP]] to i32*
|
|
; CHECK-NEXT: store atomic i32 5, i32* [[ADDR_I]] unordered, align 8
|
|
; CHECK-NEXT: fence release
|
|
; CHECK-NEXT: [[INVST:%.*]] = call {}* @llvm.invariant.start.p0i8(i64 -1, i8* [[GEP]])
|
|
; CHECK-NEXT: br label [[LOOP:%.*]]
|
|
; CHECK: loop:
|
|
; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
|
|
; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[SUM_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY]] ]
|
|
; CHECK-NEXT: [[VOLLOAD:%.*]] = load atomic i8, i8* [[VOLATILE:%.*]] unordered, align 8
|
|
; CHECK-NEXT: fence acquire
|
|
; CHECK-NEXT: [[VOLCHK:%.*]] = icmp eq i8 [[VOLLOAD]], 0
|
|
; CHECK-NEXT: [[ADDRLD:%.*]] = load atomic i32, i32* [[ADDR_I]] unordered, align 8
|
|
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[VOLCHK]], i32 0, i32 [[ADDRLD]]
|
|
; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SEL]], [[SUM]]
|
|
; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1
|
|
; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[INDVAR_NEXT]], [[N:%.*]]
|
|
; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[LOOPEXIT:%.*]]
|
|
; CHECK: loopexit:
|
|
; CHECK-NEXT: [[SUM_LCSSA:%.*]] = phi i32 [ [[SUM]], [[LOOP]] ]
|
|
; CHECK-NEXT: ret i32 [[SUM_LCSSA]]
|
|
;
|
|
entry:
|
|
%gep = getelementptr inbounds i8, i8* %addr, i64 8
|
|
%addr.i = bitcast i8* %gep to i32 *
|
|
store atomic i32 5, i32 * %addr.i unordered, align 8
|
|
fence release
|
|
%invst = call {}* @llvm.invariant.start.p0i8(i64 -1, i8* %gep)
|
|
br label %loop
|
|
|
|
loop:
|
|
%indvar = phi i32 [ %indvar.next, %loop ], [ 0, %entry ]
|
|
%sum = phi i32 [ %sum.next, %loop ], [ 0, %entry ]
|
|
%volload = load atomic i8, i8* %volatile unordered, align 8
|
|
fence acquire
|
|
%volchk = icmp eq i8 %volload, 0
|
|
%addrld = load atomic i32, i32* %addr.i unordered, align 8
|
|
%sel = select i1 %volchk, i32 0, i32 %addrld
|
|
%sum.next = add i32 %sel, %sum
|
|
%indvar.next = add i32 %indvar, 1
|
|
%cond = icmp slt i32 %indvar.next, %n
|
|
br i1 %cond, label %loop, label %loopexit
|
|
|
|
loopexit:
|
|
ret i32 %sum
|
|
}
|
|
|
|
declare void @g(i1)
|
|
|
|
@a = external global i8
|
|
|
|
; FIXME: Support hoisting invariant loads of globals.
|
|
define void @test_fence6() {
|
|
; CHECK-LABEL: @test_fence6(
|
|
; CHECK-NEXT: entry:
|
|
; CHECK-NEXT: [[I:%.*]] = call {}* @llvm.invariant.start.p0i8(i64 1, i8* @a)
|
|
; CHECK-NEXT: br label [[F:%.*]]
|
|
; CHECK: f:
|
|
; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* @a, align 1
|
|
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[TMP0]], 0
|
|
; CHECK-NEXT: [[T:%.*]] = icmp eq i8 [[TMP1]], 0
|
|
; CHECK-NEXT: tail call void @g(i1 [[T]])
|
|
; CHECK-NEXT: br label [[F]]
|
|
;
|
|
entry:
|
|
%i = call {}* @llvm.invariant.start.p0i8(i64 1, i8* @a)
|
|
br label %f
|
|
|
|
f:
|
|
%0 = load i8, i8* @a
|
|
%1 = and i8 %0, 0
|
|
%t = icmp eq i8 %1, 0
|
|
tail call void @g(i1 %t)
|
|
br label %f
|
|
}
|