llvm-project/llvm/test/CodeGen
Dan Gohman 1407484178 The list-td and list-tdrr schedulers don't yet support physreg
scheduling dependencies. Add assertion checks to help catch
this.

It appears the Mips target defaults to list-td, and it has a
regression test that uses a physreg dependence. Such code was
liable to be miscompiled, and now evokes an assertion failure.

llvm-svn: 62177
2009-01-13 20:24:13 +00:00
..
ARM Clean up some ARM GV asm printing out; minor fixes to match what gcc does. 2008-12-06 02:00:55 +00:00
Alpha Correct some thinkos in the expansion of ADD/SUB 2008-11-12 08:23:26 +00:00
CBackend Fix PR2907 by digging through constant expressions to find FP constants that 2008-10-22 04:53:16 +00:00
CPP Put CPPBackend tests into their own directory and run them only if they're 2008-07-10 22:35:32 +00:00
CellSPU Fix off-by-one error in traversing an array; this fixes a test. 2009-01-07 23:07:29 +00:00
Generic The list-td and list-tdrr schedulers don't yet support physreg 2009-01-13 20:24:13 +00:00
IA64 sabre brings to my attention that the 'tr' suffix is also obsolete 2008-05-20 21:00:03 +00:00
Mips The list-td and list-tdrr schedulers don't yet support physreg 2009-01-13 20:24:13 +00:00
PowerPC this test should not run opt -std-compile-opts, it should run 2009-01-09 05:32:00 +00:00
SPARC Add testcase for 'r' inline asm operand 2008-10-10 20:28:59 +00:00
X86 When replacing uses and the same node is reached 2009-01-13 15:17:14 +00:00
XCore Add support for ISD::TRAP to the XCore backend 2008-12-03 10:59:16 +00:00