forked from OSchip/llvm-project
1407484178
scheduling dependencies. Add assertion checks to help catch this. It appears the Mips target defaults to list-td, and it has a regression test that uses a physreg dependence. Such code was liable to be miscompiled, and now evokes an assertion failure. llvm-svn: 62177 |
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ARM | ||
Alpha | ||
CBackend | ||
CPP | ||
CellSPU | ||
Generic | ||
IA64 | ||
Mips | ||
PowerPC | ||
SPARC | ||
X86 | ||
XCore |