forked from OSchip/llvm-project
71 lines
2.2 KiB
LLVM
71 lines
2.2 KiB
LLVM
; RUN: opt %loadPolly -polly-import-jscop -polly-ast -polly-ast-detect-parallel -analyze < %s | FileCheck %s
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; RUN: opt %loadPolly -polyhedral-info -polly-check-parallel -analyze < %s | FileCheck %s -check-prefix=PINFO
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;
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; CHECK-NOT: #pragma simd{{\s*$}}
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; CHECK: #pragma simd reduction
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; CHECK: Stmt_S0(n - c1)
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; CHECK: #pragma simd{{\s*$}}
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; CHECK: Stmt_S1(n - c1)
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;
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; PINFO: for.cond2: Loop is parallel.
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; PINFO-NEXT: for.cond: Loop is not parallel.
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;
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; void rlr(int *A, long n) {
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; for (long i = 0; i < 2 * n; i++)
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; S0: A[0] += i;
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; for (long i = 0; i < 2 * n; i++)
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; S1: A[i + 1] = 1;
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; }
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;
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"
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define void @rlr(i32* %A, i32 %n) {
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entry:
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br label %for.cond
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for.cond: ; preds = %for.inc, %entry
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%i.0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
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%mul = shl nsw i32 %n, 1
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%cmp = icmp slt i32 %i.0, %mul
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br i1 %cmp, label %for.body, label %for.end
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for.body: ; preds = %for.cond
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br label %S0
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S0: ; preds = %for.body
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%tmp = load i32, i32* %A, align 4
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%add = add nsw i32 %tmp, %i.0
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store i32 %add, i32* %A, align 4
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br label %for.inc
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for.inc: ; preds = %S0
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%inc = add nsw i32 %i.0, 1
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br label %for.cond
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for.end: ; preds = %for.cond
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br label %for.cond2
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for.cond2: ; preds = %for.inc8, %for.end
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%i1.0 = phi i32 [ 0, %for.end ], [ %inc9, %for.inc8 ]
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%mul3 = shl nsw i32 %n, 1
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%cmp4 = icmp slt i32 %i1.0, %mul3
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br i1 %cmp4, label %for.body5, label %for.end10
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for.body5: ; preds = %for.cond2
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br label %S1
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S1: ; preds = %for.body5
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%add6 = add nsw i32 %i1.0, 1
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%arrayidx7 = getelementptr inbounds i32, i32* %A, i32 %add6
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store i32 1, i32* %arrayidx7, align 4
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br label %for.inc8
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for.inc8: ; preds = %S1
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%inc9 = add nsw i32 %i1.0, 1
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br label %for.cond2
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for.end10: ; preds = %for.cond2
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ret void
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}
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