forked from OSchip/llvm-project
c9c3f49993
important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. llvm-svn: 53146 |
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| .. | ||
| Makefile | ||
| Mips.h | ||
| Mips.td | ||
| MipsAsmPrinter.cpp | ||
| MipsCallingConv.td | ||
| MipsDelaySlotFiller.cpp | ||
| MipsISelDAGToDAG.cpp | ||
| MipsISelLowering.cpp | ||
| MipsISelLowering.h | ||
| MipsInstrFPU.td | ||
| MipsInstrFormats.td | ||
| MipsInstrInfo.cpp | ||
| MipsInstrInfo.h | ||
| MipsInstrInfo.td | ||
| MipsMachineFunction.h | ||
| MipsRegisterInfo.cpp | ||
| MipsRegisterInfo.h | ||
| MipsRegisterInfo.td | ||
| MipsSchedule.td | ||
| MipsSubtarget.cpp | ||
| MipsSubtarget.h | ||
| MipsTargetAsmInfo.cpp | ||
| MipsTargetAsmInfo.h | ||
| MipsTargetMachine.cpp | ||
| MipsTargetMachine.h | ||