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llvm-project/llvm/test/CodeGen/MIR/ARM
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Francis Visoiu Mistrih c71cced0aa [CodeGen] Always use `printReg` to print registers in both MIR and debug 
output

As part of the unification of the debug format and the MIR format,
always use `printReg` to print all kinds of registers.

Updated the tests using '_' instead of '%noreg' until we decide which
one we want to be the default one.

Differential Revision: https://reviews.llvm.org/D40421

llvm-svn: 319445
 		2017-11-30 16:12:24 +00:00
..
PR32721_ifcvt_triangle_unanalyzable.mir [IfConversion] Add testcases [NFC] 2017-09-20 08:23:29 +00:00
bundled-instructions.mir [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
cfi-same-value.mir
…
expected-closing-brace.mir
…
extraneous-closing-brace-error.mir
…
ifcvt_canFallThroughTo.mir [MIRPrinter] Print empty successor lists when they cannot be guessed 2017-09-19 23:34:12 +00:00
ifcvt_diamond_unanalyzable.mir [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
ifcvt_forked_diamond_unanalyzable.mir [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
ifcvt_simple_bad_zero_prob_succ.mir [IfConversion] Add testcases [NFC] 2017-09-20 08:23:29 +00:00
ifcvt_simple_unanalyzable.mir [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
ifcvt_triangleWoCvtToNextEdge.mir [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
lit.local.cfg
…
nested-instruction-bundle-error.mir
…
target-constant-pools-error.mir [MIR] Print target-specific constant pools 2017-08-02 11:09:30 +00:00