llvm-project/llvm/test/CodeGen
Craig Topper ad3d6f993d [SelectionDAG][X86][ARM][AArch64] Add ISD opcode for __builtin_parity. Expand it to shifts and xors.
Clang emits (and (ctpop X), 1) for __builtin_parity. If ctpop
isn't natively supported by the target, this leads to poor codegen
due to the expansion of ctpop being more complex than what is needed
for parity.

This adds a DAG combine to convert the pattern to ISD::PARITY
before operation legalization. Type legalization is updated
to handled Expanding and Promoting this operation. If after type
legalization, CTPOP is supported for this type, LegalizeDAG will
turn it back into CTPOP+AND. Otherwise LegalizeDAG will emit a
series of shifts and xors followed by an AND with 1.

I've avoided vectors in this patch to avoid more legalization
complexity for this patch.

X86 previously had a custom DAG combiner for this. This is now
moved to Custom lowering for the new opcode. There is a minor
regression in vector-reduce-xor-bool.ll, but a follow up patch
can easily fix that.

Fixes PR47433

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D87209
2020-09-12 11:42:18 -07:00
..
AArch64 [SelectionDAG][X86][ARM][AArch64] Add ISD opcode for __builtin_parity. Expand it to shifts and xors. 2020-09-12 11:42:18 -07:00
AMDGPU CodeGen: Require SSA to run PeepholeOptimizer 2020-09-11 18:03:04 -04:00
ARC [ARC] Update brcc test. 2020-08-28 17:07:25 -07:00
ARM [SelectionDAG][X86][ARM][AArch64] Add ISD opcode for __builtin_parity. Expand it to shifts and xors. 2020-09-12 11:42:18 -07:00
AVR
BPF BPF: add a SimplifyCFG IR pass during generic Scalar/IPO optimization 2020-08-06 13:16:00 -07:00
Generic [Intrinsics] define semantics for experimental fmax/fmin vector reductions 2020-09-12 09:10:28 -04:00
Hexagon [Hexagon] Split pair-based masked memops 2020-09-10 14:24:42 -05:00
Inputs
Lanai
MIR [MIRVRegNamer] Experimental MachineInstr stable hashing (Fowler-Noll-Vo) 2020-09-03 16:13:09 -04:00
MSP430
Mips [GlobalISel][IRTranslator] Generate better conditional branch lowering. 2020-09-09 13:16:11 -07:00
NVPTX [NVPTX] Fix typo in lit test 2020-08-17 16:02:11 -04:00
PowerPC [Power10] Enable the heuristic for Power10 and switch the sched model 2020-09-12 02:49:47 +00:00
RISCV [RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move 2020-08-27 10:32:22 +01:00
SPARC [Sparc] Add reduced funnel shift test case for PR47303 2020-09-07 16:17:31 +01:00
SystemZ [SelectionDAGBuilder] Pass fast math flags to getNode calls rather than trying to set them after the fact.: 2020-09-08 15:27:21 -07:00
Thumb
Thumb2 [ARM] Fixup single source mla reductions. 2020-09-12 14:31:26 +01:00
VE [VE] Support f128 2020-08-17 17:26:52 +09:00
WebAssembly [WebAssembly] Fix fixEndsAtEndOfFunction for try-catch 2020-09-08 09:27:40 -07:00
WinCFGuard
WinEH
X86 [SelectionDAG][X86][ARM][AArch64] Add ISD opcode for __builtin_parity. Expand it to shifts and xors. 2020-09-12 11:42:18 -07:00
XCore