forked from OSchip/llvm-project
316 lines
9.6 KiB
C++
316 lines
9.6 KiB
C++
//===- AArch64LegalizerInfo.cpp ----------------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the Machinelegalizer class for
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/// AArch64.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "AArch64LegalizerInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/IR/Type.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/Target/TargetOpcodes.h"
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using namespace llvm;
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#ifndef LLVM_BUILD_GLOBAL_ISEL
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#error "You shouldn't build this"
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#endif
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AArch64LegalizerInfo::AArch64LegalizerInfo() {
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using namespace TargetOpcode;
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const LLT p0 = LLT::pointer(0, 64);
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const LLT s1 = LLT::scalar(1);
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const LLT s8 = LLT::scalar(8);
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const LLT s16 = LLT::scalar(16);
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const LLT s32 = LLT::scalar(32);
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const LLT s64 = LLT::scalar(64);
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const LLT v2s32 = LLT::vector(2, 32);
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const LLT v4s32 = LLT::vector(4, 32);
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const LLT v2s64 = LLT::vector(2, 64);
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for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR, G_SHL}) {
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// These operations naturally get the right answer when used on
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// GPR32, even if the actual type is narrower.
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for (auto Ty : {s32, s64, v2s32, v4s32, v2s64})
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setAction({BinOp, Ty}, Legal);
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for (auto Ty : {s1, s8, s16})
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setAction({BinOp, Ty}, WidenScalar);
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}
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setAction({G_GEP, p0}, Legal);
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setAction({G_GEP, 1, s64}, Legal);
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for (auto Ty : {s1, s8, s16, s32})
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setAction({G_GEP, 1, Ty}, WidenScalar);
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setAction({G_PTR_MASK, p0}, Legal);
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for (unsigned BinOp : {G_LSHR, G_ASHR, G_SDIV, G_UDIV}) {
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for (auto Ty : {s32, s64})
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setAction({BinOp, Ty}, Legal);
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for (auto Ty : {s1, s8, s16})
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setAction({BinOp, Ty}, WidenScalar);
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}
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for (unsigned BinOp : {G_SREM, G_UREM})
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for (auto Ty : { s1, s8, s16, s32, s64 })
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setAction({BinOp, Ty}, Lower);
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for (unsigned Op : {G_SMULO, G_UMULO})
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setAction({Op, s64}, Lower);
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for (unsigned Op : {G_UADDE, G_USUBE, G_SADDO, G_SSUBO, G_SMULH, G_UMULH}) {
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for (auto Ty : { s32, s64 })
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setAction({Op, Ty}, Legal);
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setAction({Op, 1, s1}, Legal);
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}
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for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
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for (auto Ty : {s32, s64})
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setAction({BinOp, Ty}, Legal);
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for (unsigned BinOp : {G_FREM, G_FPOW}) {
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setAction({BinOp, s32}, Libcall);
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setAction({BinOp, s64}, Libcall);
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}
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for (auto Ty : {s32, s64, p0}) {
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setAction({G_INSERT, Ty}, Legal);
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setAction({G_INSERT, 1, Ty}, Legal);
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}
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for (auto Ty : {s1, s8, s16}) {
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setAction({G_INSERT, Ty}, WidenScalar);
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setAction({G_INSERT, 1, Ty}, Legal);
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// FIXME: Can't widen the sources because that violates the constraints on
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// G_INSERT (It seems entirely reasonable that inputs shouldn't overlap).
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}
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for (unsigned MemOp : {G_LOAD, G_STORE}) {
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for (auto Ty : {s8, s16, s32, s64, p0, v2s32})
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setAction({MemOp, Ty}, Legal);
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setAction({MemOp, s1}, WidenScalar);
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// And everything's fine in addrspace 0.
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setAction({MemOp, 1, p0}, Legal);
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}
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// Constants
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for (auto Ty : {s32, s64}) {
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setAction({TargetOpcode::G_CONSTANT, Ty}, Legal);
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setAction({TargetOpcode::G_FCONSTANT, Ty}, Legal);
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}
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setAction({G_CONSTANT, p0}, Legal);
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for (auto Ty : {s1, s8, s16})
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setAction({TargetOpcode::G_CONSTANT, Ty}, WidenScalar);
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setAction({TargetOpcode::G_FCONSTANT, s16}, WidenScalar);
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setAction({G_ICMP, s1}, Legal);
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setAction({G_ICMP, 1, s32}, Legal);
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setAction({G_ICMP, 1, s64}, Legal);
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setAction({G_ICMP, 1, p0}, Legal);
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for (auto Ty : {s1, s8, s16}) {
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setAction({G_ICMP, 1, Ty}, WidenScalar);
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}
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setAction({G_FCMP, s1}, Legal);
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setAction({G_FCMP, 1, s32}, Legal);
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setAction({G_FCMP, 1, s64}, Legal);
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// Extensions
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for (auto Ty : { s1, s8, s16, s32, s64 }) {
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setAction({G_ZEXT, Ty}, Legal);
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setAction({G_SEXT, Ty}, Legal);
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setAction({G_ANYEXT, Ty}, Legal);
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}
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for (auto Ty : { s1, s8, s16, s32 }) {
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setAction({G_ZEXT, 1, Ty}, Legal);
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setAction({G_SEXT, 1, Ty}, Legal);
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setAction({G_ANYEXT, 1, Ty}, Legal);
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}
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setAction({G_FPEXT, s64}, Legal);
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setAction({G_FPEXT, 1, s32}, Legal);
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// Truncations
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for (auto Ty : { s16, s32 })
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setAction({G_FPTRUNC, Ty}, Legal);
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for (auto Ty : { s32, s64 })
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setAction({G_FPTRUNC, 1, Ty}, Legal);
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for (auto Ty : { s1, s8, s16, s32 })
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setAction({G_TRUNC, Ty}, Legal);
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for (auto Ty : { s8, s16, s32, s64 })
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setAction({G_TRUNC, 1, Ty}, Legal);
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// Conversions
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for (auto Ty : { s32, s64 }) {
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setAction({G_FPTOSI, 0, Ty}, Legal);
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setAction({G_FPTOUI, 0, Ty}, Legal);
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setAction({G_SITOFP, 1, Ty}, Legal);
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setAction({G_UITOFP, 1, Ty}, Legal);
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}
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for (auto Ty : { s1, s8, s16 }) {
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setAction({G_FPTOSI, 0, Ty}, WidenScalar);
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setAction({G_FPTOUI, 0, Ty}, WidenScalar);
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setAction({G_SITOFP, 1, Ty}, WidenScalar);
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setAction({G_UITOFP, 1, Ty}, WidenScalar);
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}
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for (auto Ty : { s32, s64 }) {
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setAction({G_FPTOSI, 1, Ty}, Legal);
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setAction({G_FPTOUI, 1, Ty}, Legal);
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setAction({G_SITOFP, 0, Ty}, Legal);
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setAction({G_UITOFP, 0, Ty}, Legal);
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}
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// Control-flow
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for (auto Ty : {s1, s8, s16, s32})
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setAction({G_BRCOND, Ty}, Legal);
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setAction({G_BRINDIRECT, p0}, Legal);
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// Select
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for (auto Ty : {s1, s8, s16})
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setAction({G_SELECT, Ty}, WidenScalar);
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for (auto Ty : {s32, s64, p0})
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setAction({G_SELECT, Ty}, Legal);
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setAction({G_SELECT, 1, s1}, Legal);
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// Pointer-handling
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setAction({G_FRAME_INDEX, p0}, Legal);
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setAction({G_GLOBAL_VALUE, p0}, Legal);
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for (auto Ty : {s1, s8, s16, s32, s64})
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setAction({G_PTRTOINT, 0, Ty}, Legal);
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setAction({G_PTRTOINT, 1, p0}, Legal);
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setAction({G_INTTOPTR, 0, p0}, Legal);
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setAction({G_INTTOPTR, 1, s64}, Legal);
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// Casts for 32 and 64-bit width type are just copies.
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for (auto Ty : {s1, s8, s16, s32, s64}) {
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setAction({G_BITCAST, 0, Ty}, Legal);
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setAction({G_BITCAST, 1, Ty}, Legal);
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}
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// For the sake of copying bits around, the type does not really
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// matter as long as it fits a register.
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for (int EltSize = 8; EltSize <= 64; EltSize *= 2) {
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setAction({G_BITCAST, 0, LLT::vector(128/EltSize, EltSize)}, Legal);
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setAction({G_BITCAST, 1, LLT::vector(128/EltSize, EltSize)}, Legal);
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if (EltSize >= 64)
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continue;
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setAction({G_BITCAST, 0, LLT::vector(64/EltSize, EltSize)}, Legal);
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setAction({G_BITCAST, 1, LLT::vector(64/EltSize, EltSize)}, Legal);
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if (EltSize >= 32)
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continue;
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setAction({G_BITCAST, 0, LLT::vector(32/EltSize, EltSize)}, Legal);
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setAction({G_BITCAST, 1, LLT::vector(32/EltSize, EltSize)}, Legal);
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}
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setAction({G_VASTART, p0}, Legal);
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// va_list must be a pointer, but most sized types are pretty easy to handle
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// as the destination.
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setAction({G_VAARG, 1, p0}, Legal);
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for (auto Ty : {s8, s16, s32, s64, p0})
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setAction({G_VAARG, Ty}, Custom);
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computeTables();
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}
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bool AArch64LegalizerInfo::legalizeCustom(MachineInstr &MI,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const {
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switch (MI.getOpcode()) {
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default:
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// No idea what to do.
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return false;
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case TargetOpcode::G_VAARG:
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return legalizeVaArg(MI, MRI, MIRBuilder);
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}
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llvm_unreachable("expected switch to return");
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}
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bool AArch64LegalizerInfo::legalizeVaArg(MachineInstr &MI,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const {
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MIRBuilder.setInstr(MI);
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MachineFunction &MF = MIRBuilder.getMF();
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unsigned Align = MI.getOperand(2).getImm();
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unsigned Dst = MI.getOperand(0).getReg();
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unsigned ListPtr = MI.getOperand(1).getReg();
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LLT PtrTy = MRI.getType(ListPtr);
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LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits());
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const unsigned PtrSize = PtrTy.getSizeInBits() / 8;
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unsigned List = MRI.createGenericVirtualRegister(PtrTy);
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MIRBuilder.buildLoad(
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List, ListPtr,
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*MF.getMachineMemOperand(MachinePointerInfo(), MachineMemOperand::MOLoad,
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PtrSize, /* Align = */ PtrSize));
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unsigned DstPtr;
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if (Align > PtrSize) {
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// Realign the list to the actual required alignment.
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unsigned AlignMinus1 = MRI.createGenericVirtualRegister(IntPtrTy);
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MIRBuilder.buildConstant(AlignMinus1, Align - 1);
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unsigned ListTmp = MRI.createGenericVirtualRegister(PtrTy);
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MIRBuilder.buildGEP(ListTmp, List, AlignMinus1);
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DstPtr = MRI.createGenericVirtualRegister(PtrTy);
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MIRBuilder.buildPtrMask(DstPtr, ListTmp, Log2_64(Align));
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} else
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DstPtr = List;
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uint64_t ValSize = MRI.getType(Dst).getSizeInBits() / 8;
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MIRBuilder.buildLoad(
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Dst, DstPtr,
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*MF.getMachineMemOperand(MachinePointerInfo(), MachineMemOperand::MOLoad,
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ValSize, std::max(Align, PtrSize)));
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unsigned SizeReg = MRI.createGenericVirtualRegister(IntPtrTy);
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MIRBuilder.buildConstant(SizeReg, alignTo(ValSize, PtrSize));
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unsigned NewList = MRI.createGenericVirtualRegister(PtrTy);
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MIRBuilder.buildGEP(NewList, DstPtr, SizeReg);
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MIRBuilder.buildStore(
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NewList, ListPtr,
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*MF.getMachineMemOperand(MachinePointerInfo(), MachineMemOperand::MOStore,
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PtrSize, /* Align = */ PtrSize));
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MI.eraseFromParent();
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return true;
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}
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