forked from OSchip/llvm-project
71 lines
3.2 KiB
LLVM
71 lines
3.2 KiB
LLVM
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
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declare <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8>, <16 x i8>)
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; CHECK-LABEL: fun1:
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; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
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define i32 @fun1() {
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entry:
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%vtbl1.i.1 = tail call <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8> <i8 0, i8 16, i8 19, i8 4, i8 -65, i8 -65, i8 -71, i8 -71, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8> undef)
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%vuzp.i212.1 = shufflevector <16 x i8> %vtbl1.i.1, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%scevgep = getelementptr <8 x i8>, <8 x i8>* undef, i64 1
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store <8 x i8> %vuzp.i212.1, <8 x i8>* %scevgep, align 1
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ret i32 undef
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}
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; CHECK-LABEL: fun2:
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; CHECK: uzp2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
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define i32 @fun2() {
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entry:
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%vtbl1.i.1 = tail call <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8> <i8 0, i8 16, i8 19, i8 4, i8 -65, i8 -65, i8 -71, i8 -71, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8> undef)
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%vuzp.i212.1 = shufflevector <16 x i8> %vtbl1.i.1, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%scevgep = getelementptr <8 x i8>, <8 x i8>* undef, i64 1
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store <8 x i8> %vuzp.i212.1, <8 x i8>* %scevgep, align 1
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ret i32 undef
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}
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; CHECK-LABEL: fun3:
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; CHECK-NOT: uzp1
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define i32 @fun3() {
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entry:
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%vtbl1.i.1 = tail call <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8> <i8 0, i8 16, i8 19, i8 4, i8 -65, i8 -65, i8 -71, i8 -71, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8> undef)
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%vuzp.i212.1 = shufflevector <16 x i8> %vtbl1.i.1, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 15>
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%scevgep = getelementptr <8 x i8>, <8 x i8>* undef, i64 1
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store <8 x i8> %vuzp.i212.1, <8 x i8>* %scevgep, align 1
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ret i32 undef
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}
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; CHECK-LABEL: fun4:
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; CHECK-NOT: uzp2
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define i32 @fun4() {
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entry:
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%vtbl1.i.1 = tail call <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8> <i8 0, i8 16, i8 19, i8 4, i8 -65, i8 -65, i8 -71, i8 -71, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8> undef)
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%vuzp.i212.1 = shufflevector <16 x i8> %vtbl1.i.1, <16 x i8> undef, <8 x i32> <i32 3, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%scevgep = getelementptr <8 x i8>, <8 x i8>* undef, i64 1
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store <8 x i8> %vuzp.i212.1, <8 x i8>* %scevgep, align 1
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ret i32 undef
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}
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; CHECK-LABEL: pr36582:
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; Check that this does not ICE.
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define void @pr36582(i8* %p1, i32* %p2) {
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entry:
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%x = bitcast i8* %p1 to <8 x i8>*
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%wide.vec = load <8 x i8>, <8 x i8>* %x, align 1
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%strided.vec = shufflevector <8 x i8> %wide.vec, <8 x i8> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%y = zext <4 x i8> %strided.vec to <4 x i32>
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%z = bitcast i32* %p2 to <4 x i32>*
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store <4 x i32> %y, <4 x i32>* %z, align 4
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ret void
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}
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; Check that this pattern is recognized as a VZIP and
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; that the vector blend transform does not scramble the pattern.
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; CHECK-LABEL: vzipNoBlend:
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; CHECK: zip1
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define <8 x i8> @vzipNoBlend(<8 x i8>* %A, <8 x i16>* %B) nounwind {
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%t = load <8 x i8>, <8 x i8>* %A
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%vzip = shufflevector <8 x i8> %t, <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef>, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
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ret <8 x i8> %vzip
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}
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