forked from OSchip/llvm-project
37 lines
992 B
YAML
37 lines
992 B
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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define void @FMADDSrrr_fpr() { ret void }
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...
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---
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name: FMADDSrrr_fpr
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: fpr }
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- { id: 3, class: fpr }
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body: |
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bb.0:
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liveins: $w0, $w1, $w2
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; CHECK-LABEL: name: FMADDSrrr_fpr
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $w1
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; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $w2
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; CHECK: [[FMADDSrrr:%[0-9]+]]:fpr32 = FMADDSrrr [[COPY]], [[COPY1]], [[COPY2]]
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; CHECK: $w0 = COPY [[FMADDSrrr]]
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%0(s32) = COPY $w0
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%1(s32) = COPY $w1
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%2(s32) = COPY $w2
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%3(s32) = G_FMA %0, %1, %2
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$w0 = COPY %3
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...
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