forked from OSchip/llvm-project
174 lines
4.6 KiB
C++
174 lines
4.6 KiB
C++
//=====-- R600Subtarget.h - Define Subtarget for AMDGPU R600 ----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//==-----------------------------------------------------------------------===//
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//
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/// \file
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/// AMDGPU R600 specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H
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#define LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H
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#include "AMDGPUSubtarget.h"
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#include "R600FrameLowering.h"
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#include "R600ISelLowering.h"
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#include "R600InstrInfo.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
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namespace llvm {
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class MCInstrInfo;
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} // namespace llvm
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#define GET_SUBTARGETINFO_HEADER
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#include "R600GenSubtargetInfo.inc"
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namespace llvm {
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class R600Subtarget final : public R600GenSubtargetInfo,
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public AMDGPUSubtarget {
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private:
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R600InstrInfo InstrInfo;
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R600FrameLowering FrameLowering;
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bool FMA;
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bool CaymanISA;
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bool CFALUBug;
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bool HasVertexCache;
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bool R600ALUInst;
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bool FP64;
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short TexVTXClauseSize;
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Generation Gen;
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R600TargetLowering TLInfo;
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InstrItineraryData InstrItins;
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SelectionDAGTargetInfo TSInfo;
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public:
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R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
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const TargetMachine &TM);
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const R600InstrInfo *getInstrInfo() const override { return &InstrInfo; }
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const R600FrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const R600TargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const R600RegisterInfo *getRegisterInfo() const override {
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return &InstrInfo.getRegisterInfo();
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}
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const InstrItineraryData *getInstrItineraryData() const override {
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return &InstrItins;
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}
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// Nothing implemented, just prevent crashes on use.
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const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
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Generation getGeneration() const {
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return Gen;
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}
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Align getStackAlignment() const { return Align(4); }
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R600Subtarget &initializeSubtargetDependencies(const Triple &TT,
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StringRef GPU, StringRef FS);
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bool hasBFE() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasBFI() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasBCNT(unsigned Size) const {
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if (Size == 32)
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return (getGeneration() >= EVERGREEN);
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return false;
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}
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bool hasBORROW() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasCARRY() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasCaymanISA() const {
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return CaymanISA;
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}
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bool hasFFBL() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasFFBH() const {
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return (getGeneration() >= EVERGREEN);
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}
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bool hasFMA() const { return FMA; }
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bool hasCFAluBug() const { return CFALUBug; }
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bool hasVertexCache() const { return HasVertexCache; }
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short getTexVTXClauseSize() const { return TexVTXClauseSize; }
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bool enableMachineScheduler() const override {
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return true;
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}
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bool enableSubRegLiveness() const override {
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return true;
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}
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/// \returns Maximum number of work groups per compute unit supported by the
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/// subtarget and limited by given \p FlatWorkGroupSize.
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unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const override {
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return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(this, FlatWorkGroupSize);
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}
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/// \returns Minimum flat work group size supported by the subtarget.
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unsigned getMinFlatWorkGroupSize() const override {
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return AMDGPU::IsaInfo::getMinFlatWorkGroupSize(this);
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}
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/// \returns Maximum flat work group size supported by the subtarget.
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unsigned getMaxFlatWorkGroupSize() const override {
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return AMDGPU::IsaInfo::getMaxFlatWorkGroupSize(this);
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}
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/// \returns Number of waves per execution unit required to support the given
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/// \p FlatWorkGroupSize.
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unsigned
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getWavesPerEUForWorkGroup(unsigned FlatWorkGroupSize) const override {
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return AMDGPU::IsaInfo::getWavesPerEUForWorkGroup(this, FlatWorkGroupSize);
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}
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/// \returns Minimum number of waves per execution unit supported by the
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/// subtarget.
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unsigned getMinWavesPerEU() const override {
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return AMDGPU::IsaInfo::getMinWavesPerEU(this);
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}
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H
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