forked from OSchip/llvm-project
318 lines
11 KiB
C++
318 lines
11 KiB
C++
//===-- LanaiISelDAGToDAG.cpp - A dag to dag inst selector for Lanai ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the Lanai target.
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//
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//===----------------------------------------------------------------------===//
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#include "Lanai.h"
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#include "LanaiMachineFunctionInfo.h"
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#include "LanaiRegisterInfo.h"
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#include "LanaiSubtarget.h"
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#include "LanaiTargetMachine.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/IR/CFG.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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#define DEBUG_TYPE "lanai-isel"
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// LanaiDAGToDAGISel - Lanai specific code to select Lanai machine
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// instructions for SelectionDAG operations.
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//===----------------------------------------------------------------------===//
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namespace {
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class LanaiDAGToDAGISel : public SelectionDAGISel {
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public:
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explicit LanaiDAGToDAGISel(LanaiTargetMachine &TargetMachine)
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: SelectionDAGISel(TargetMachine) {}
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bool runOnMachineFunction(MachineFunction &MF) override {
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return SelectionDAGISel::runOnMachineFunction(MF);
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}
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// Pass Name
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StringRef getPassName() const override {
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return "Lanai DAG->DAG Pattern Instruction Selection";
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}
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bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintCode,
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std::vector<SDValue> &OutOps) override;
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private:
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// Include the pieces autogenerated from the target description.
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#include "LanaiGenDAGISel.inc"
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// Instruction Selection not handled by the auto-generated tablgen
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void Select(SDNode *N) override;
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// Support functions for the opcodes of Instruction Selection
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// not handled by the auto-generated tablgen
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void selectFrameIndex(SDNode *N);
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// Complex Pattern for address selection.
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bool selectAddrRi(SDValue Addr, SDValue &Base, SDValue &Offset,
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SDValue &AluOp);
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bool selectAddrRr(SDValue Addr, SDValue &R1, SDValue &R2, SDValue &AluOp);
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bool selectAddrSls(SDValue Addr, SDValue &Offset);
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bool selectAddrSpls(SDValue Addr, SDValue &Base, SDValue &Offset,
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SDValue &AluOp);
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// getI32Imm - Return a target constant with the specified value, of type i32.
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inline SDValue getI32Imm(unsigned Imm, const SDLoc &DL) {
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return CurDAG->getTargetConstant(Imm, DL, MVT::i32);
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}
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private:
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bool selectAddrRiSpls(SDValue Addr, SDValue &Base, SDValue &Offset,
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SDValue &AluOp, bool RiMode);
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};
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bool canBeRepresentedAsSls(const ConstantSDNode &CN) {
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// Fits in 21-bit signed immediate and two low-order bits are zero.
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return isInt<21>(CN.getSExtValue()) && ((CN.getSExtValue() & 0x3) == 0);
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}
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} // namespace
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// Helper functions for ComplexPattern used on LanaiInstrInfo
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// Used on Lanai Load/Store instructions.
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bool LanaiDAGToDAGISel::selectAddrSls(SDValue Addr, SDValue &Offset) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr)) {
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SDLoc DL(Addr);
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// Loading from a constant address.
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if (canBeRepresentedAsSls(*CN)) {
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int32_t Imm = CN->getSExtValue();
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Offset = CurDAG->getTargetConstant(Imm, DL, CN->getValueType(0));
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return true;
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}
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}
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if (Addr.getOpcode() == ISD::OR &&
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Addr.getOperand(1).getOpcode() == LanaiISD::SMALL) {
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Offset = Addr.getOperand(1).getOperand(0);
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return true;
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}
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return false;
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}
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bool LanaiDAGToDAGISel::selectAddrRiSpls(SDValue Addr, SDValue &Base,
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SDValue &Offset, SDValue &AluOp,
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bool RiMode) {
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SDLoc DL(Addr);
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr)) {
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if (RiMode) {
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// Fits in 16-bit signed immediate.
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if (isInt<16>(CN->getSExtValue())) {
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int16_t Imm = CN->getSExtValue();
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Offset = CurDAG->getTargetConstant(Imm, DL, CN->getValueType(0));
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Base = CurDAG->getRegister(Lanai::R0, CN->getValueType(0));
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AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32);
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return true;
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}
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// Allow SLS to match if the constant doesn't fit in 16 bits but can be
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// represented as an SLS.
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if (canBeRepresentedAsSls(*CN))
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return false;
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} else {
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// Fits in 10-bit signed immediate.
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if (isInt<10>(CN->getSExtValue())) {
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int16_t Imm = CN->getSExtValue();
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Offset = CurDAG->getTargetConstant(Imm, DL, CN->getValueType(0));
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Base = CurDAG->getRegister(Lanai::R0, CN->getValueType(0));
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AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32);
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return true;
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}
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}
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}
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// if Address is FI, get the TargetFrameIndex.
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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Base = CurDAG->getTargetFrameIndex(
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FIN->getIndex(),
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getTargetLowering()->getPointerTy(CurDAG->getDataLayout()));
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Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
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AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32);
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return true;
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}
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// Skip direct calls
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if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress))
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return false;
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// Address of the form imm + reg
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ISD::NodeType AluOperator = static_cast<ISD::NodeType>(Addr.getOpcode());
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if (AluOperator == ISD::ADD) {
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AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32);
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// Addresses of the form FI+const
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
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if ((RiMode && isInt<16>(CN->getSExtValue())) ||
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(!RiMode && isInt<10>(CN->getSExtValue()))) {
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// If the first operand is a FI, get the TargetFI Node
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if (FrameIndexSDNode *FIN =
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dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
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Base = CurDAG->getTargetFrameIndex(
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FIN->getIndex(),
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getTargetLowering()->getPointerTy(CurDAG->getDataLayout()));
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} else {
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Base = Addr.getOperand(0);
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}
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Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i32);
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return true;
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}
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}
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// Let SLS match SMALL instead of RI.
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if (AluOperator == ISD::OR && RiMode &&
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Addr.getOperand(1).getOpcode() == LanaiISD::SMALL)
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return false;
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, DL, MVT::i32);
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AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32);
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return true;
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}
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bool LanaiDAGToDAGISel::selectAddrRi(SDValue Addr, SDValue &Base,
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SDValue &Offset, SDValue &AluOp) {
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return selectAddrRiSpls(Addr, Base, Offset, AluOp, /*RiMode=*/true);
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}
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bool LanaiDAGToDAGISel::selectAddrSpls(SDValue Addr, SDValue &Base,
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SDValue &Offset, SDValue &AluOp) {
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return selectAddrRiSpls(Addr, Base, Offset, AluOp, /*RiMode=*/false);
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}
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bool LanaiDAGToDAGISel::selectAddrRr(SDValue Addr, SDValue &R1, SDValue &R2,
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SDValue &AluOp) {
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// if Address is FI, get the TargetFrameIndex.
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if (Addr.getOpcode() == ISD::FrameIndex)
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return false;
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// Skip direct calls
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if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress))
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return false;
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// Address of the form OP + OP
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ISD::NodeType AluOperator = static_cast<ISD::NodeType>(Addr.getOpcode());
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LPAC::AluCode AluCode = LPAC::isdToLanaiAluCode(AluOperator);
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if (AluCode != LPAC::UNKNOWN) {
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// Skip addresses of the form FI OP const
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
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if (isInt<16>(CN->getSExtValue()))
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return false;
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// Skip addresses with hi/lo operands
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if (Addr.getOperand(0).getOpcode() == LanaiISD::HI ||
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Addr.getOperand(0).getOpcode() == LanaiISD::LO ||
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Addr.getOperand(0).getOpcode() == LanaiISD::SMALL ||
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Addr.getOperand(1).getOpcode() == LanaiISD::HI ||
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Addr.getOperand(1).getOpcode() == LanaiISD::LO ||
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Addr.getOperand(1).getOpcode() == LanaiISD::SMALL)
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return false;
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// Addresses of the form register OP register
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R1 = Addr.getOperand(0);
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R2 = Addr.getOperand(1);
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AluOp = CurDAG->getTargetConstant(AluCode, SDLoc(Addr), MVT::i32);
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return true;
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}
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// Skip addresses with zero offset
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return false;
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}
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bool LanaiDAGToDAGISel::SelectInlineAsmMemoryOperand(
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const SDValue &Op, unsigned ConstraintCode, std::vector<SDValue> &OutOps) {
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SDValue Op0, Op1, AluOp;
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switch (ConstraintCode) {
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default:
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return true;
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case InlineAsm::Constraint_m: // memory
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if (!selectAddrRr(Op, Op0, Op1, AluOp) &&
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!selectAddrRi(Op, Op0, Op1, AluOp))
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return true;
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break;
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}
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OutOps.push_back(Op0);
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OutOps.push_back(Op1);
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OutOps.push_back(AluOp);
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return false;
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}
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// Select instructions not customized! Used for
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// expanded, promoted and normal instructions
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void LanaiDAGToDAGISel::Select(SDNode *Node) {
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unsigned Opcode = Node->getOpcode();
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// Dump information about the Node being selected
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DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
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// If we have a custom node, we already have selected!
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if (Node->isMachineOpcode()) {
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DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
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return;
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}
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// Instruction Selection not handled by the auto-generated
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// tablegen selection should be handled here.
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switch (Opcode) {
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case ISD::FrameIndex:
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selectFrameIndex(Node);
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return;
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default:
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break;
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}
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// Select the default instruction
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SelectCode(Node);
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}
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void LanaiDAGToDAGISel::selectFrameIndex(SDNode *Node) {
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SDLoc DL(Node);
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SDValue Imm = CurDAG->getTargetConstant(0, DL, MVT::i32);
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int FI = dyn_cast<FrameIndexSDNode>(Node)->getIndex();
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EVT VT = Node->getValueType(0);
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SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
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unsigned Opc = Lanai::ADD_I_LO;
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if (Node->hasOneUse()) {
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CurDAG->SelectNodeTo(Node, Opc, VT, TFI, Imm);
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return;
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}
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ReplaceNode(Node, CurDAG->getMachineNode(Opc, DL, VT, TFI, Imm));
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}
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// createLanaiISelDag - This pass converts a legalized DAG into a
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// Lanai-specific DAG, ready for instruction scheduling.
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FunctionPass *llvm::createLanaiISelDag(LanaiTargetMachine &TM) {
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return new LanaiDAGToDAGISel(TM);
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}
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