forked from OSchip/llvm-project
187 lines
5.6 KiB
C++
187 lines
5.6 KiB
C++
//===-- BPFISelDAGToDAG.cpp - A dag to dag inst selector for BPF ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a DAG pattern matching instruction selector for BPF,
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// converting from a legalized dag to a BPF dag.
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//
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//===----------------------------------------------------------------------===//
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#include "BPF.h"
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#include "BPFRegisterInfo.h"
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#include "BPFSubtarget.h"
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#include "BPFTargetMachine.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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#define DEBUG_TYPE "bpf-isel"
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// Instruction Selector Implementation
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namespace {
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class BPFDAGToDAGISel : public SelectionDAGISel {
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public:
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explicit BPFDAGToDAGISel(BPFTargetMachine &TM) : SelectionDAGISel(TM) {}
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StringRef getPassName() const override {
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return "BPF DAG->DAG Pattern Instruction Selection";
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}
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private:
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// Include the pieces autogenerated from the target description.
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#include "BPFGenDAGISel.inc"
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void Select(SDNode *N) override;
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// Complex Pattern for address selection.
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bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset);
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bool SelectFIAddr(SDValue Addr, SDValue &Base, SDValue &Offset);
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};
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}
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// ComplexPattern used on BPF Load/Store instructions
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bool BPFDAGToDAGISel::SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset) {
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// if Address is FI, get the TargetFrameIndex.
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SDLoc DL(Addr);
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
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Offset = CurDAG->getTargetConstant(0, DL, MVT::i64);
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return true;
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}
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress)
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return false;
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// Addresses of the form Addr+const or Addr|const
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if (CurDAG->isBaseWithConstantOffset(Addr)) {
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
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if (isInt<32>(CN->getSExtValue())) {
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// If the first operand is a FI, get the TargetFI Node
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if (FrameIndexSDNode *FIN =
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dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
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else
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Base = Addr.getOperand(0);
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Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i64);
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return true;
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}
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}
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, DL, MVT::i64);
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return true;
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}
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// ComplexPattern used on BPF FI instruction
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bool BPFDAGToDAGISel::SelectFIAddr(SDValue Addr, SDValue &Base, SDValue &Offset) {
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SDLoc DL(Addr);
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if (!CurDAG->isBaseWithConstantOffset(Addr))
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return false;
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// Addresses of the form Addr+const or Addr|const
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
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if (isInt<32>(CN->getSExtValue())) {
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// If the first operand is a FI, get the TargetFI Node
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if (FrameIndexSDNode *FIN =
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dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
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else
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return false;
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Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i64);
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return true;
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}
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return false;
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}
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void BPFDAGToDAGISel::Select(SDNode *Node) {
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unsigned Opcode = Node->getOpcode();
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// Dump information about the Node being selected
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DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
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// If we have a custom node, we already have selected!
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if (Node->isMachineOpcode()) {
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DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
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return;
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}
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// tablegen selection should be handled here.
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switch (Opcode) {
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default: break;
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case ISD::SDIV: {
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DebugLoc Empty;
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const DebugLoc &DL = Node->getDebugLoc();
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if (DL != Empty)
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errs() << "Error at line " << DL.getLine() << ": ";
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else
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errs() << "Error: ";
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errs() << "Unsupport signed division for DAG: ";
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Node->dump(CurDAG);
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errs() << "Please convert to unsigned div/mod.\n";
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break;
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}
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case ISD::INTRINSIC_W_CHAIN: {
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unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
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switch (IntNo) {
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case Intrinsic::bpf_load_byte:
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case Intrinsic::bpf_load_half:
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case Intrinsic::bpf_load_word: {
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SDLoc DL(Node);
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SDValue Chain = Node->getOperand(0);
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SDValue N1 = Node->getOperand(1);
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SDValue Skb = Node->getOperand(2);
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SDValue N3 = Node->getOperand(3);
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SDValue R6Reg = CurDAG->getRegister(BPF::R6, MVT::i64);
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Chain = CurDAG->getCopyToReg(Chain, DL, R6Reg, Skb, SDValue());
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Node = CurDAG->UpdateNodeOperands(Node, Chain, N1, R6Reg, N3);
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break;
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}
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}
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break;
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}
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case ISD::FrameIndex: {
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int FI = cast<FrameIndexSDNode>(Node)->getIndex();
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EVT VT = Node->getValueType(0);
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SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
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unsigned Opc = BPF::MOV_rr;
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if (Node->hasOneUse()) {
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CurDAG->SelectNodeTo(Node, Opc, VT, TFI);
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return;
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}
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ReplaceNode(Node, CurDAG->getMachineNode(Opc, SDLoc(Node), VT, TFI));
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return;
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}
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}
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// Select the default instruction
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SelectCode(Node);
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}
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FunctionPass *llvm::createBPFISelDag(BPFTargetMachine &TM) {
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return new BPFDAGToDAGISel(TM);
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}
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