forked from OSchip/llvm-project
143 lines
4.5 KiB
C++
143 lines
4.5 KiB
C++
//===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file includes code for rendering MCInst instances as AT&T-style
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// assembly.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "asm-printer"
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#include "llvm/MC/MCInst.h"
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#include "X86ATTAsmPrinter.h"
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#include "llvm/Target/TargetAsmInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/FormattedStream.h"
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using namespace llvm;
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// Include the auto-generated portion of the assembly writer.
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#define MachineInstr MCInst
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#define NO_ASM_WRITER_BOILERPLATE
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#include "X86GenAsmWriter.inc"
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#undef MachineInstr
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void X86ATTAsmPrinter::printSSECC(const MCInst *MI, unsigned Op) {
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switch (MI->getOperand(Op).getImm()) {
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default: llvm_unreachable("Invalid ssecc argument!");
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case 0: O << "eq"; break;
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case 1: O << "lt"; break;
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case 2: O << "le"; break;
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case 3: O << "unord"; break;
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case 4: O << "neq"; break;
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case 5: O << "nlt"; break;
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case 6: O << "nle"; break;
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case 7: O << "ord"; break;
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}
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}
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void X86ATTAsmPrinter::printPICLabel(const MCInst *MI, unsigned Op) {
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llvm_unreachable("This is only used for MOVPC32r,"
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"should lower before asm printing!");
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}
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/// print_pcrel_imm - This is used to print an immediate value that ends up
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/// being encoded as a pc-relative value. These print slightly differently, for
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/// example, a $ is not emitted.
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void X86ATTAsmPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isImm())
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O << Op.getImm();
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else if (Op.isMBBLabel())
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// FIXME: Keep in sync with printBasicBlockLabel. printBasicBlockLabel
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// should eventually call into this code, not the other way around.
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O << TAI->getPrivateGlobalPrefix() << "BB" << Op.getMBBLabelFunction()
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<< '_' << Op.getMBBLabelBlock();
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else
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llvm_unreachable("Unknown pcrel immediate operand");
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}
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void X86ATTAsmPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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const char *Modifier) {
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assert(Modifier == 0 && "Modifiers should not be used");
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isReg()) {
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O << '%';
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unsigned Reg = Op.getReg();
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#if 0
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if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
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MVT VT = (strcmp(Modifier+6,"64") == 0) ?
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MVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? MVT::i32 :
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((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
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Reg = getX86SubSuperRegister(Reg, VT);
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}
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#endif
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O << TRI->getAsmName(Reg);
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return;
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} else if (Op.isImm()) {
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//if (!Modifier || (strcmp(Modifier, "debug") && strcmp(Modifier, "mem")))
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O << '$';
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O << Op.getImm();
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return;
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}
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O << "<<UNKNOWN OPERAND KIND>>";
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}
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void X86ATTAsmPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) {
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const MCOperand &BaseReg = MI->getOperand(Op);
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const MCOperand &IndexReg = MI->getOperand(Op+2);
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const MCOperand &DispSpec = MI->getOperand(Op+3);
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if (DispSpec.isImm()) {
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int64_t DispVal = DispSpec.getImm();
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if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
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O << DispVal;
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} else {
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llvm_unreachable("non-immediate displacement for LEA?");
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//assert(DispSpec.isGlobal() || DispSpec.isCPI() ||
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// DispSpec.isJTI() || DispSpec.isSymbol());
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//printOperand(MI, Op+3, "mem");
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}
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if (IndexReg.getReg() || BaseReg.getReg()) {
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// There are cases where we can end up with ESP/RSP in the indexreg slot.
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// If this happens, swap the base/index register to support assemblers that
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// don't work when the index is *SP.
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// FIXME: REMOVE THIS.
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assert(IndexReg.getReg() != X86::ESP && IndexReg.getReg() != X86::RSP);
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O << '(';
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if (BaseReg.getReg())
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printOperand(MI, Op);
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if (IndexReg.getReg()) {
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O << ',';
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printOperand(MI, Op+2);
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unsigned ScaleVal = MI->getOperand(Op+1).getImm();
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if (ScaleVal != 1)
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O << ',' << ScaleVal;
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}
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O << ')';
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}
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}
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void X86ATTAsmPrinter::printMemReference(const MCInst *MI, unsigned Op) {
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const MCOperand &Segment = MI->getOperand(Op+4);
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if (Segment.getReg()) {
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printOperand(MI, Op+4);
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O << ':';
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}
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printLeaMemReference(MI, Op);
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}
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