forked from OSchip/llvm-project
33185e66f2
This diff modifies the tablegen specification and code generation for BitEnumAttr attributes in MLIR Operation Definition Specification (ODS) files. Specifically: - there is a new tablegen class for "none" values (i.e. no bits set) - single-bit enum cases are specified via bit index (i.e. [0, 31]) instead of the resulting enum integer value - there is a new tablegen class to represent a "grouped" bitwise OR of other enum values This diff is intended as an initial step towards improving "fastmath" optimization support in MLIR, to allow more precise control of whether certain floating point optimizations are applied in MLIR passes. "Fast" math options for floating point MLIR operations would (following subsequent RFC and discussion) be specified by using the improved enum bit support in this diff. For example, a "fast" enum value would act as an alias for a group of other cases (e.g. finite-math-only, no-signed-zeros, etc.), in a way that is similar to support in C/C++ compilers (clang, gcc). Reviewed By: rriddle Differential Revision: https://reviews.llvm.org/D117029 |
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| .. | ||
| mlir-cpu-runner | ||
| mlir-linalg-ods-gen | ||
| mlir-lsp-server | ||
| mlir-opt | ||
| mlir-pdll | ||
| mlir-reduce | ||
| mlir-shlib | ||
| mlir-spirv-cpu-runner | ||
| mlir-tblgen | ||
| mlir-translate | ||
| mlir-vulkan-runner | ||
| CMakeLists.txt | ||