forked from OSchip/llvm-project
584 lines
26 KiB
LLVM
584 lines
26 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -mcpu=tahiti -mattr=-fp32-denormals,+fast-fmaf -fp-contract=on < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH-STRICT,GCN-FLUSH,SI-FLUSH,GCN-FLUSH-FASTFMA,GCN-FLUSH-FASTFMA-STRICT,SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -mcpu=tahiti -mattr=+fp32-denormals,+fast-fmaf -fp-contract=on < %s | FileCheck -check-prefixes=GCN,GCN-DENORM-STRICT,GCN-DENORM,SI-DENORM,GCN-DENORM-FASTFMA,GCN-DENORM-FASTFMA-STRICT,SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -mcpu=verde -mattr=-fp32-denormals,-fast-fmaf -fp-contract=on < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH-STRICT,GCN-FLUSH,SI-FLUSH,GCN-FLUSH-SLOWFMA,GCN-FLUSH-SLOWFMA-STRICT,SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -mcpu=verde -mattr=+fp32-denormals,-fast-fmaf -fp-contract=on < %s | FileCheck -check-prefixes=GCN,GCN-DENORM-STRICT,GCN-DENORM,SI-DENORM,GCN-DENORM-SLOWFMA,GCN-DENORM-SLOWFMA-STRICT,SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -mcpu=tahiti -mattr=-fp32-denormals,+fast-fmaf -fp-contract=fast < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH-CONTRACT,GCN-FLUSH,SI-FLUSH,GCN-FLUSH-FASTFMA,GCN-FLUSH-FASTFMA-CONTRACT,SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -mcpu=tahiti -mattr=+fp32-denormals,+fast-fmaf -fp-contract=fast < %s | FileCheck -check-prefixes=GCN,GCN-DENORM-CONTRACT,GCN-DENORM,SI-DENORM,GCN-DENORM-FASTFMA,GCN-DENORM-FASTFMA-CONTRACT,SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -mcpu=verde -mattr=-fp32-denormals,-fast-fmaf -fp-contract=fast < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH-CONTRACT,GCN-FLUSH,SI-FLUSH,GCN-FLUSH-SLOWFMA,GCN-FLUSH-SLOWFMA-CONTRACT,SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -verify-machineinstrs -mcpu=verde -mattr=+fp32-denormals,-fast-fmaf -fp-contract=fast < %s | FileCheck -check-prefixes=GCN,GCN-DENORM-CONTRACT,GCN-DENORM,SI-DENORM,GCN-DENORM-SLOWFMA,GCN-DENORM-SLOWFMA-CONTRACT,SI %s
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; Test all permutations of: fp32 denormals, fast fp contract, fp contract enabled for fmuladd, fmaf fast/slow.
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target triple = "amdgcn--"
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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declare float @llvm.fmuladd.f32(float, float, float) #1
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declare half @llvm.fmuladd.f16(half, half, half) #1
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declare float @llvm.fabs.f32(float) #1
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; GCN-LABEL: {{^}}fmuladd_f32:
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; GCN-FLUSH: v_mac_f32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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; GCN-DENORM-FASTFMA: v_fma_f32 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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; GCN-DENORM-SLOWFMA: v_mul_f32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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; GCN-DENORM-SLOWFMA: v_add_f32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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define amdgpu_kernel void @fmuladd_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
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float addrspace(1)* %in2, float addrspace(1)* %in3) #0 {
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%r0 = load float, float addrspace(1)* %in1
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%r1 = load float, float addrspace(1)* %in2
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%r2 = load float, float addrspace(1)* %in3
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%r3 = tail call float @llvm.fmuladd.f32(float %r0, float %r1, float %r2)
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store float %r3, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}fmul_fadd_f32:
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; GCN-FLUSH: v_mac_f32
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; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32
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; GCN-DENORM-SLOWFMA-CONTRACT: v_mul_f32_e32
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; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32
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; GCN-DENORM-STRICT: v_mul_f32_e32
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; GCN-DENORM-STRICT: v_add_f32_e32
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define amdgpu_kernel void @fmul_fadd_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
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float addrspace(1)* %in2, float addrspace(1)* %in3) #0 {
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%r0 = load volatile float, float addrspace(1)* %in1
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%r1 = load volatile float, float addrspace(1)* %in2
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%r2 = load volatile float, float addrspace(1)* %in3
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%mul = fmul float %r0, %r1
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%add = fadd float %mul, %r2
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store float %add, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}fmuladd_2.0_a_b_f32
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; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
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; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
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; GCN-FLUSH: v_mac_f32_e32 [[R2]], 2.0, [[R1]]
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; SI-FLUSH: buffer_store_dword [[R2]]
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; VI-FLUSH: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]]
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; GCN-DENORM-FASTFMA: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, [[R2]]
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; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
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; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]]
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; SI-DENORM buffer_store_dword [[RESULT]]
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; VI-DENORM: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define amdgpu_kernel void @fmuladd_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
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%r1 = load volatile float, float addrspace(1)* %gep.0
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%r2 = load volatile float, float addrspace(1)* %gep.1
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%r3 = tail call float @llvm.fmuladd.f32(float 2.0, float %r1, float %r2)
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store float %r3, float addrspace(1)* %gep.out
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ret void
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}
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; GCN-LABEL: {{^}}fmuladd_a_2.0_b_f32
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; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
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; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
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; GCN-FLUSH: v_mac_f32_e32 [[R2]], 2.0, [[R1]]
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; SI-FLUSH: buffer_store_dword [[R2]]
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; VI-FLUSH: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]]
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; GCN-DENORM-FASTFMA: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, [[R2]]
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; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
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; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]]
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; SI-DENORM: buffer_store_dword [[RESULT]]
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; VI-DENORM: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define amdgpu_kernel void @fmuladd_a_2.0_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
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%r1 = load volatile float, float addrspace(1)* %gep.0
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%r2 = load volatile float, float addrspace(1)* %gep.1
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%r3 = tail call float @llvm.fmuladd.f32(float %r1, float 2.0, float %r2)
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store float %r3, float addrspace(1)* %gep.out
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ret void
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}
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; GCN-LABEL: {{^}}fadd_a_a_b_f32:
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; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
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; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
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; GCN-FLUSH: v_mac_f32_e32 [[R2]], 2.0, [[R1]]
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; SI-FLUSH: buffer_store_dword [[R2]]
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; VI-FLUSH: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]]
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; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, [[R2]]
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; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
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; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]]
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; GCN-DENORM-STRICT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
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; GCN-DENORM-STRICT: v_add_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]]
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; SI-DENORM: buffer_store_dword [[RESULT]]
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; VI-DENORM: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define amdgpu_kernel void @fadd_a_a_b_f32(float addrspace(1)* %out,
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float addrspace(1)* %in1,
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float addrspace(1)* %in2) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
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%r0 = load volatile float, float addrspace(1)* %gep.0
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%r1 = load volatile float, float addrspace(1)* %gep.1
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%add.0 = fadd float %r0, %r0
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%add.1 = fadd float %add.0, %r1
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store float %add.1, float addrspace(1)* %gep.out
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ret void
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}
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; GCN-LABEL: {{^}}fadd_b_a_a_f32:
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; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
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; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
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; GCN-FLUSH: v_mac_f32_e32 [[R2]], 2.0, [[R1]]
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; SI-FLUSH: buffer_store_dword [[R2]]
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; VI-FLUSH: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]]
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; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, [[R2]]
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; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
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; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32 [[RESULT:v[0-9]+]], [[R2]], [[TMP]]
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; GCN-DENORM-STRICT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
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; GCN-DENORM-STRICT: v_add_f32_e32 [[RESULT:v[0-9]+]], [[R2]], [[TMP]]
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; SI-DENORM: buffer_store_dword [[RESULT]]
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; VI-DENORM: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define amdgpu_kernel void @fadd_b_a_a_f32(float addrspace(1)* %out,
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float addrspace(1)* %in1,
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float addrspace(1)* %in2) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
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%r0 = load volatile float, float addrspace(1)* %gep.0
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%r1 = load volatile float, float addrspace(1)* %gep.1
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%add.0 = fadd float %r0, %r0
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%add.1 = fadd float %r1, %add.0
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store float %add.1, float addrspace(1)* %gep.out
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ret void
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}
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; GCN-LABEL: {{^}}fmuladd_neg_2.0_a_b_f32
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; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
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; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
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; GCN-FLUSH: v_mac_f32_e32 [[R2]], -2.0, [[R1]]
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; GCN-DENORM-FASTFMA: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], -2.0, [[R2]]
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; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
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; GCN-DENORM-SLOWFMA: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[R2]], [[TMP]]
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; SI-DENORM: buffer_store_dword [[RESULT]]
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; VI-DENORM: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define amdgpu_kernel void @fmuladd_neg_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
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%r1 = load volatile float, float addrspace(1)* %gep.0
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%r2 = load volatile float, float addrspace(1)* %gep.1
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%r3 = tail call float @llvm.fmuladd.f32(float -2.0, float %r1, float %r2)
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store float %r3, float addrspace(1)* %gep.out
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ret void
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}
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; GCN-LABEL: {{^}}fmuladd_neg_2.0_neg_a_b_f32
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; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
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; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
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; GCN-FLUSH: v_mac_f32_e32 [[R2]], 2.0, [[R1]]
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; SI-FLUSH: buffer_store_dword [[R2]]
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; VI-FLUSH: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]]
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; GCN-DENORM-FASTFMA: v_fma_f32 [[RESULT:v[0-9]+]], -[[R1]], -2.0, [[R2]]
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; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
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; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[RESULT:v[0-9]+]], [[R2]], [[TMP]]
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; SI-DENORM: buffer_store_dword [[RESULT]]
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; VI-DENORM: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define amdgpu_kernel void @fmuladd_neg_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
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%r1 = load volatile float, float addrspace(1)* %gep.0
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%r2 = load volatile float, float addrspace(1)* %gep.1
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%r1.fneg = fsub float -0.000000e+00, %r1
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%r3 = tail call float @llvm.fmuladd.f32(float -2.0, float %r1.fneg, float %r2)
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store float %r3, float addrspace(1)* %gep.out
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ret void
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}
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; GCN-LABEL: {{^}}fmuladd_2.0_neg_a_b_f32:
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; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
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; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
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; GCN-FLUSH: v_mac_f32_e32 [[R2]], -2.0, [[R1]]
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; SI-FLUSH: buffer_store_dword [[R2]]
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; VI-FLUSH: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]]
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; GCN-DENORM-FASTFMA: v_fma_f32 [[RESULT:v[0-9]+]], -[[R1]], 2.0, [[R2]]
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; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
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; GCN-DENORM-SLOWFMA: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[R2]], [[TMP]]
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; SI-DENORM: buffer_store_dword [[RESULT]]
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; VI-DENORM: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define amdgpu_kernel void @fmuladd_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
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%r1 = load volatile float, float addrspace(1)* %gep.0
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%r2 = load volatile float, float addrspace(1)* %gep.1
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%r1.fneg = fsub float -0.000000e+00, %r1
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%r3 = tail call float @llvm.fmuladd.f32(float 2.0, float %r1.fneg, float %r2)
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store float %r3, float addrspace(1)* %gep.out
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ret void
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}
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; GCN-LABEL: {{^}}fmuladd_2.0_a_neg_b_f32:
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; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
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; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
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; GCN-FLUSH: v_mad_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, -[[R2]]
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; SI-FLUSH: buffer_store_dword [[RESULT]]
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; VI-FLUSH: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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; GCN-DENORM-FASTFMA: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, -[[R2]]
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; GCN-DENORM-SLOWFMA: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
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; GCN-DENORM-SLOWFMA: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]]
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; SI-DENORM: buffer_store_dword [[RESULT]]
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; VI-DENORM: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define amdgpu_kernel void @fmuladd_2.0_a_neg_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
|
|
%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
|
|
%gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
|
|
|
|
%r1 = load volatile float, float addrspace(1)* %gep.0
|
|
%r2 = load volatile float, float addrspace(1)* %gep.1
|
|
|
|
%r2.fneg = fsub float -0.000000e+00, %r2
|
|
|
|
%r3 = tail call float @llvm.fmuladd.f32(float 2.0, float %r1, float %r2.fneg)
|
|
store float %r3, float addrspace(1)* %gep.out
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}mad_sub_f32:
|
|
; GCN: {{buffer|flat}}_load_dword [[REGA:v[0-9]+]]
|
|
; GCN: {{buffer|flat}}_load_dword [[REGB:v[0-9]+]]
|
|
; GCN: {{buffer|flat}}_load_dword [[REGC:v[0-9]+]]
|
|
; GCN-FLUSH: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -[[REGC]]
|
|
|
|
; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -[[REGC]]
|
|
|
|
; GCN-DENORM-SLOWFMA-CONTRACT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
|
|
; GCN-DENORM-SLOWFMA-CONTRACT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[REGC]]
|
|
|
|
; GCN-DENORM-STRICT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
|
|
; GCN-DENORM-STRICT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[REGC]]
|
|
|
|
; SI: buffer_store_dword [[RESULT]]
|
|
; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
|
|
define amdgpu_kernel void @mad_sub_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #0 {
|
|
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
|
|
%tid.ext = sext i32 %tid to i64
|
|
%gep0 = getelementptr float, float addrspace(1)* %ptr, i64 %tid.ext
|
|
%add1 = add i64 %tid.ext, 1
|
|
%gep1 = getelementptr float, float addrspace(1)* %ptr, i64 %add1
|
|
%add2 = add i64 %tid.ext, 2
|
|
%gep2 = getelementptr float, float addrspace(1)* %ptr, i64 %add2
|
|
%outgep = getelementptr float, float addrspace(1)* %out, i64 %tid.ext
|
|
%a = load volatile float, float addrspace(1)* %gep0, align 4
|
|
%b = load volatile float, float addrspace(1)* %gep1, align 4
|
|
%c = load volatile float, float addrspace(1)* %gep2, align 4
|
|
%mul = fmul float %a, %b
|
|
%sub = fsub float %mul, %c
|
|
store float %sub, float addrspace(1)* %outgep, align 4
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}mad_sub_inv_f32:
|
|
; GCN: {{buffer|flat}}_load_dword [[REGA:v[0-9]+]]
|
|
; GCN: {{buffer|flat}}_load_dword [[REGB:v[0-9]+]]
|
|
; GCN: {{buffer|flat}}_load_dword [[REGC:v[0-9]+]]
|
|
|
|
; GCN-FLUSH: v_mad_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], [[REGC]]
|
|
|
|
; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], [[REGC]]
|
|
|
|
; GCN-DENORM-SLOWFMA-CONTRACT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
|
|
; GCN-DENORM-SLOWFMA-CONTRACT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[REGC]], [[TMP]]
|
|
|
|
; GCN-DENORM-STRICT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
|
|
; GCN-DENORM-STRICT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[REGC]], [[TMP]]
|
|
|
|
; SI: buffer_store_dword [[RESULT]]
|
|
; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
|
|
define amdgpu_kernel void @mad_sub_inv_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #0 {
|
|
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
|
|
%tid.ext = sext i32 %tid to i64
|
|
%gep0 = getelementptr float, float addrspace(1)* %ptr, i64 %tid.ext
|
|
%add1 = add i64 %tid.ext, 1
|
|
%gep1 = getelementptr float, float addrspace(1)* %ptr, i64 %add1
|
|
%add2 = add i64 %tid.ext, 2
|
|
%gep2 = getelementptr float, float addrspace(1)* %ptr, i64 %add2
|
|
%outgep = getelementptr float, float addrspace(1)* %out, i64 %tid.ext
|
|
%a = load volatile float, float addrspace(1)* %gep0, align 4
|
|
%b = load volatile float, float addrspace(1)* %gep1, align 4
|
|
%c = load volatile float, float addrspace(1)* %gep2, align 4
|
|
%mul = fmul float %a, %b
|
|
%sub = fsub float %c, %mul
|
|
store float %sub, float addrspace(1)* %outgep, align 4
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}mad_sub_fabs_f32:
|
|
; GCN: {{buffer|flat}}_load_dword [[REGA:v[0-9]+]]
|
|
; GCN: {{buffer|flat}}_load_dword [[REGB:v[0-9]+]]
|
|
; GCN: {{buffer|flat}}_load_dword [[REGC:v[0-9]+]]
|
|
; GCN-FLUSH: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -|[[REGC]]|
|
|
|
|
; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -|[[REGC]]|
|
|
|
|
; GCN-DENORM-SLOWFMA-CONTRACT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
|
|
; GCN-DENORM-SLOWFMA-CONTRACT: v_sub_f32_e64 [[RESULT:v[0-9]+]], [[TMP]], |[[REGC]]|
|
|
|
|
; GCN-DENORM-STRICT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
|
|
; GCN-DENORM-STRICT: v_sub_f32_e64 [[RESULT:v[0-9]+]], [[TMP]], |[[REGC]]|
|
|
|
|
; SI: buffer_store_dword [[RESULT]]
|
|
; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
|
|
define amdgpu_kernel void @mad_sub_fabs_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #0 {
|
|
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
|
|
%tid.ext = sext i32 %tid to i64
|
|
%gep0 = getelementptr float, float addrspace(1)* %ptr, i64 %tid.ext
|
|
%add1 = add i64 %tid.ext, 1
|
|
%gep1 = getelementptr float, float addrspace(1)* %ptr, i64 %add1
|
|
%add2 = add i64 %tid.ext, 2
|
|
%gep2 = getelementptr float, float addrspace(1)* %ptr, i64 %add2
|
|
%outgep = getelementptr float, float addrspace(1)* %out, i64 %tid.ext
|
|
%a = load volatile float, float addrspace(1)* %gep0, align 4
|
|
%b = load volatile float, float addrspace(1)* %gep1, align 4
|
|
%c = load volatile float, float addrspace(1)* %gep2, align 4
|
|
%c.abs = call float @llvm.fabs.f32(float %c) #0
|
|
%mul = fmul float %a, %b
|
|
%sub = fsub float %mul, %c.abs
|
|
store float %sub, float addrspace(1)* %outgep, align 4
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}mad_sub_fabs_inv_f32:
|
|
; GCN: {{buffer|flat}}_load_dword [[REGA:v[0-9]+]]
|
|
; GCN: {{buffer|flat}}_load_dword [[REGB:v[0-9]+]]
|
|
; GCN: {{buffer|flat}}_load_dword [[REGC:v[0-9]+]]
|
|
; GCN-FLUSH: v_mad_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], |[[REGC]]|
|
|
|
|
; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], |[[REGC]]|
|
|
|
|
; GCN-DENORM-SLOWFMA-CONTRACT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
|
|
; GCN-DENORM-SLOWFMA-CONTRACT: v_sub_f32_e64 [[RESULT:v[0-9]+]], |[[REGC]]|, [[TMP]]
|
|
|
|
; GCN-DENORM-STRICT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
|
|
; GCN-DENORM-STRICT: v_sub_f32_e64 [[RESULT:v[0-9]+]], |[[REGC]]|, [[TMP]]
|
|
|
|
; SI: buffer_store_dword [[RESULT]]
|
|
; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
|
|
define amdgpu_kernel void @mad_sub_fabs_inv_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #0 {
|
|
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
|
|
%tid.ext = sext i32 %tid to i64
|
|
%gep0 = getelementptr float, float addrspace(1)* %ptr, i64 %tid.ext
|
|
%add1 = add i64 %tid.ext, 1
|
|
%gep1 = getelementptr float, float addrspace(1)* %ptr, i64 %add1
|
|
%add2 = add i64 %tid.ext, 2
|
|
%gep2 = getelementptr float, float addrspace(1)* %ptr, i64 %add2
|
|
%outgep = getelementptr float, float addrspace(1)* %out, i64 %tid.ext
|
|
%a = load volatile float, float addrspace(1)* %gep0, align 4
|
|
%b = load volatile float, float addrspace(1)* %gep1, align 4
|
|
%c = load volatile float, float addrspace(1)* %gep2, align 4
|
|
%c.abs = call float @llvm.fabs.f32(float %c) #0
|
|
%mul = fmul float %a, %b
|
|
%sub = fsub float %c.abs, %mul
|
|
store float %sub, float addrspace(1)* %outgep, align 4
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}neg_neg_mad_f32:
|
|
; GCN: {{buffer|flat}}_load_dword [[REGA:v[0-9]+]]
|
|
; GCN: {{buffer|flat}}_load_dword [[REGB:v[0-9]+]]
|
|
; GCN: {{buffer|flat}}_load_dword [[REGC:v[0-9]+]]
|
|
|
|
; GCN-FLUSH: v_mac_f32_e32 [[REGC]], [[REGA]], [[REGB]]
|
|
; SI-FLUSH: buffer_store_dword [[REGC]]
|
|
; VI-FLUSH: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[REGC]]
|
|
|
|
; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], [[REGC]]
|
|
|
|
; GCN-DENORM-SLOWFMA-CONTRACT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
|
|
; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32 [[RESULT:v[0-9]+]], [[REGC]], [[TMP]]
|
|
|
|
; GCN-DENORM-STRICT: v_mul_f32_e32 [[TMP:v[0-9]+]], [[REGA]], [[REGB]]
|
|
; GCN-DENORM-STRICT: v_add_f32_e32 [[RESULT:v[0-9]+]], [[REGC]], [[TMP]]
|
|
|
|
; SI-DENORM: buffer_store_dword [[RESULT]]
|
|
; VI-DENORM: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
|
|
define amdgpu_kernel void @neg_neg_mad_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #0 {
|
|
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
|
|
%tid.ext = sext i32 %tid to i64
|
|
%gep0 = getelementptr float, float addrspace(1)* %ptr, i64 %tid.ext
|
|
%add1 = add i64 %tid.ext, 1
|
|
%gep1 = getelementptr float, float addrspace(1)* %ptr, i64 %add1
|
|
%add2 = add i64 %tid.ext, 2
|
|
%gep2 = getelementptr float, float addrspace(1)* %ptr, i64 %add2
|
|
%outgep = getelementptr float, float addrspace(1)* %out, i64 %tid.ext
|
|
%a = load volatile float, float addrspace(1)* %gep0, align 4
|
|
%b = load volatile float, float addrspace(1)* %gep1, align 4
|
|
%c = load volatile float, float addrspace(1)* %gep2, align 4
|
|
%nega = fsub float -0.000000e+00, %a
|
|
%negb = fsub float -0.000000e+00, %b
|
|
%mul = fmul float %nega, %negb
|
|
%sub = fadd float %mul, %c
|
|
store float %sub, float addrspace(1)* %outgep, align 4
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}mad_fabs_sub_f32:
|
|
; GCN: {{buffer|flat}}_load_dword [[REGA:v[0-9]+]]
|
|
; GCN: {{buffer|flat}}_load_dword [[REGB:v[0-9]+]]
|
|
; GCN: {{buffer|flat}}_load_dword [[REGC:v[0-9]+]]
|
|
; GCN-FLUSH: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], |[[REGB]]|, -[[REGC]]
|
|
|
|
; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], [[REGA]], |[[REGB]]|, -[[REGC]]
|
|
|
|
; GCN-DENORM-SLOWFMA-CONTRACT: v_mul_f32_e64 [[TMP:v[0-9]+]], [[REGA]], |[[REGB]]|
|
|
; GCN-DENORM-SLOWFMA-CONTRACT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[REGC]]
|
|
|
|
; GCN-DENORM-STRICT: v_mul_f32_e64 [[TMP:v[0-9]+]], [[REGA]], |[[REGB]]|
|
|
; GCN-DENORM-STRICT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[REGC]]
|
|
|
|
; SI: buffer_store_dword [[RESULT]]
|
|
; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
|
|
define amdgpu_kernel void @mad_fabs_sub_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #0 {
|
|
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
|
|
%tid.ext = sext i32 %tid to i64
|
|
%gep0 = getelementptr float, float addrspace(1)* %ptr, i64 %tid.ext
|
|
%add1 = add i64 %tid.ext, 1
|
|
%gep1 = getelementptr float, float addrspace(1)* %ptr, i64 %add1
|
|
%add2 = add i64 %tid.ext, 2
|
|
%gep2 = getelementptr float, float addrspace(1)* %ptr, i64 %add2
|
|
%outgep = getelementptr float, float addrspace(1)* %out, i64 %tid.ext
|
|
%a = load volatile float, float addrspace(1)* %gep0, align 4
|
|
%b = load volatile float, float addrspace(1)* %gep1, align 4
|
|
%c = load volatile float, float addrspace(1)* %gep2, align 4
|
|
%b.abs = call float @llvm.fabs.f32(float %b) #0
|
|
%mul = fmul float %a, %b.abs
|
|
%sub = fsub float %mul, %c
|
|
store float %sub, float addrspace(1)* %outgep, align 4
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}fsub_c_fadd_a_a_f32:
|
|
; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
|
|
; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
|
|
; GCN-FLUSH: v_mac_f32_e32 [[R2]], -2.0, [[R1]]
|
|
; SI-FLUSH: buffer_store_dword [[R2]]
|
|
; VI-FLUSH: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[R2]]
|
|
|
|
; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], -2.0, [[R2]]
|
|
|
|
; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
|
|
; GCN-DENORM-SLOWFMA-CONTRACT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[R2]], [[TMP]]
|
|
|
|
; GCN-DENORM-STRICT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
|
|
; GCN-DENORM-STRICT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[R2]], [[TMP]]
|
|
|
|
; SI-DENORM: buffer_store_dword [[RESULT]]
|
|
; VI-DENORM: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
|
|
define amdgpu_kernel void @fsub_c_fadd_a_a_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
|
%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
|
|
%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
|
|
%gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
|
|
|
|
%r1 = load volatile float, float addrspace(1)* %gep.0
|
|
%r2 = load volatile float, float addrspace(1)* %gep.1
|
|
|
|
%add = fadd float %r1, %r1
|
|
%r3 = fsub float %r2, %add
|
|
|
|
store float %r3, float addrspace(1)* %gep.out
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}fsub_fadd_a_a_c_f32:
|
|
; GCN: {{buffer|flat}}_load_dword [[R1:v[0-9]+]],
|
|
; GCN: {{buffer|flat}}_load_dword [[R2:v[0-9]+]],
|
|
; GCN-FLUSH: v_mad_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, -[[R2]]
|
|
|
|
; GCN-DENORM-FASTFMA-CONTRACT: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, -[[R2]]
|
|
|
|
; GCN-DENORM-SLOWFMA-CONTRACT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
|
|
; GCN-DENORM-SLOWFMA-CONTRACT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]]
|
|
|
|
; GCN-DENORM-STRICT: v_add_f32_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
|
|
; GCN-DENORM-STRICT: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]]
|
|
|
|
; SI: buffer_store_dword [[RESULT]]
|
|
; VI: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
|
|
define amdgpu_kernel void @fsub_fadd_a_a_c_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
|
%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
|
|
%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
|
|
%gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
|
|
|
|
%r1 = load volatile float, float addrspace(1)* %gep.0
|
|
%r2 = load volatile float, float addrspace(1)* %gep.1
|
|
|
|
%add = fadd float %r1, %r1
|
|
%r3 = fsub float %add, %r2
|
|
|
|
store float %r3, float addrspace(1)* %gep.out
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { nounwind }
|
|
attributes #1 = { nounwind readnone }
|