forked from OSchip/llvm-project
455 lines
12 KiB
LLVM
455 lines
12 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -amdgpu-early-ifcvt=1 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; XUN: llc -march=amdgcn -mcpu=tonga -amdgpu-early-ifcvt=1 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; FIXME: This leaves behind a now unnecessary and with exec
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; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]]
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; GCN: v_cmp_neq_f32_e32 vcc, 1.0, [[VAL]]
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; GCN: v_add_f32_e32 [[ADD:v[0-9]+]], [[VAL]], [[VAL]]
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; GCN: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], [[ADD]], [[VAL]], vcc
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; GCN: buffer_store_dword [[RESULT]]
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define amdgpu_kernel void @test_vccnz_ifcvt_triangle(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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entry:
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%v = load float, float addrspace(1)* %in
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%cc = fcmp oeq float %v, 1.000000e+00
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br i1 %cc, label %if, label %endif
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if:
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%u = fadd float %v, %v
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br label %endif
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endif:
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%r = phi float [ %v, %entry ], [ %u, %if ]
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store float %r, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}test_vccnz_ifcvt_diamond:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]]
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; GCN: v_cmp_neq_f32_e32 vcc, 1.0, [[VAL]]
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; GCN-DAG: v_add_f32_e32 [[ADD:v[0-9]+]], [[VAL]], [[VAL]]
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; GCN-DAG: v_mul_f32_e32 [[MUL:v[0-9]+]], [[VAL]], [[VAL]]
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; GCN: v_cndmask_b32_e32 [[RESULT:v[0-9]+]], [[ADD]], [[MUL]], vcc
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; GCN: buffer_store_dword [[RESULT]]
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define amdgpu_kernel void @test_vccnz_ifcvt_diamond(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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entry:
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%v = load float, float addrspace(1)* %in
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%cc = fcmp oeq float %v, 1.000000e+00
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br i1 %cc, label %if, label %else
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if:
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%u0 = fadd float %v, %v
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br label %endif
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else:
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%u1 = fmul float %v, %v
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br label %endif
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endif:
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%r = phi float [ %u0, %if ], [ %u1, %else ]
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store float %r, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle_vcc_clobber:
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; GCN: ; clobber vcc
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; GCN: v_cmp_neq_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 1.0
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; GCN: v_add_i32_e32 v{{[0-9]+}}, vcc
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; GCN: s_mov_b64 vcc, [[CMP]]
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; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, vcc
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define amdgpu_kernel void @test_vccnz_ifcvt_triangle_vcc_clobber(i32 addrspace(1)* %out, i32 addrspace(1)* %in, float %k) #0 {
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entry:
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%v = load i32, i32 addrspace(1)* %in
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%cc = fcmp oeq float %k, 1.000000e+00
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br i1 %cc, label %if, label %endif
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if:
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call void asm "; clobber $0", "~{VCC}"() #0
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%u = add i32 %v, %v
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br label %endif
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endif:
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%r = phi i32 [ %v, %entry ], [ %u, %if ]
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store i32 %r, i32 addrspace(1)* %out
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ret void
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}
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; Longest chain of cheap instructions to convert
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; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle_max_cheap:
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; GCN: v_mul_f32
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; GCN: v_mul_f32
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; GCN: v_mul_f32
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; GCN: v_mul_f32
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; GCN: v_mul_f32
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; GCN: v_mul_f32
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; GCN: v_mul_f32
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; GCN: v_mul_f32
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; GCN: v_mul_f32
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; GCN: v_cndmask_b32_e32
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define amdgpu_kernel void @test_vccnz_ifcvt_triangle_max_cheap(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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entry:
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%v = load float, float addrspace(1)* %in
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%cc = fcmp oeq float %v, 1.000000e+00
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br i1 %cc, label %if, label %endif
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if:
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%u.0 = fmul float %v, %v
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%u.1 = fmul float %v, %u.0
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%u.2 = fmul float %v, %u.1
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%u.3 = fmul float %v, %u.2
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%u.4 = fmul float %v, %u.3
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%u.5 = fmul float %v, %u.4
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%u.6 = fmul float %v, %u.5
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%u.7 = fmul float %v, %u.6
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%u.8 = fmul float %v, %u.7
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br label %endif
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endif:
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%r = phi float [ %v, %entry ], [ %u.8, %if ]
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store float %r, float addrspace(1)* %out
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ret void
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}
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; Short chain of cheap instructions to not convert
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; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle_min_expensive:
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; GCN: s_cbranch_vccnz [[ENDIF:BB[0-9]+_[0-9]+]]
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; GCN: v_mul_f32
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; GCN: v_mul_f32
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; GCN: v_mul_f32
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; GCN: v_mul_f32
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; GCN: v_mul_f32
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; GCN: v_mul_f32
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; GCN: v_mul_f32
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; GCN: v_mul_f32
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; GCN: v_mul_f32
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; GCN: v_mul_f32
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; GCN: [[ENDIF]]:
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; GCN: buffer_store_dword
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define amdgpu_kernel void @test_vccnz_ifcvt_triangle_min_expensive(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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entry:
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%v = load float, float addrspace(1)* %in
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%cc = fcmp oeq float %v, 1.000000e+00
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br i1 %cc, label %if, label %endif
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if:
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%u.0 = fmul float %v, %v
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%u.1 = fmul float %v, %u.0
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%u.2 = fmul float %v, %u.1
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%u.3 = fmul float %v, %u.2
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%u.4 = fmul float %v, %u.3
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%u.5 = fmul float %v, %u.4
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%u.6 = fmul float %v, %u.5
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%u.7 = fmul float %v, %u.6
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%u.8 = fmul float %v, %u.7
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%u.9 = fmul float %v, %u.8
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br label %endif
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endif:
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%r = phi float [ %v, %entry ], [ %u.9, %if ]
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store float %r, float addrspace(1)* %out
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ret void
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}
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; Should still branch over fdiv expansion
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; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle_expensive:
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; GCN: v_cmp_neq_f32_e32
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; GCN: s_cbranch_vccnz [[ENDIF:BB[0-9]+_[0-9]+]]
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; GCN: v_div_scale_f32
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; GCN: [[ENDIF]]:
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; GCN: buffer_store_dword
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define amdgpu_kernel void @test_vccnz_ifcvt_triangle_expensive(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
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entry:
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%v = load float, float addrspace(1)* %in
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%cc = fcmp oeq float %v, 1.000000e+00
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br i1 %cc, label %if, label %endif
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if:
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%u = fdiv float %v, %v
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br label %endif
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endif:
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%r = phi float [ %v, %entry ], [ %u, %if ]
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store float %r, float addrspace(1)* %out
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ret void
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}
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; vcc branch with SGPR inputs
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; GCN-LABEL: {{^}}test_vccnz_sgpr_ifcvt_triangle:
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; GCN: v_cmp_neq_f32_e64
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; GCN: s_cbranch_vccnz [[ENDIF:BB[0-9]+_[0-9]+]]
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; GCN: s_add_i32
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; GCN: [[ENDIF]]:
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; GCN: buffer_store_dword
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define amdgpu_kernel void @test_vccnz_sgpr_ifcvt_triangle(i32 addrspace(1)* %out, i32 addrspace(2)* %in, float %cnd) #0 {
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entry:
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%v = load i32, i32 addrspace(2)* %in
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%cc = fcmp oeq float %cnd, 1.000000e+00
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br i1 %cc, label %if, label %endif
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if:
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%u = add i32 %v, %v
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br label %endif
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endif:
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%r = phi i32 [ %v, %entry ], [ %u, %if ]
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store i32 %r, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle_constant_load:
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; GCN: v_cndmask_b32
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define amdgpu_kernel void @test_vccnz_ifcvt_triangle_constant_load(float addrspace(1)* %out, float addrspace(2)* %in) #0 {
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entry:
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%v = load float, float addrspace(2)* %in
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%cc = fcmp oeq float %v, 1.000000e+00
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br i1 %cc, label %if, label %endif
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if:
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%u = fadd float %v, %v
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br label %endif
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endif:
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%r = phi float [ %v, %entry ], [ %u, %if ]
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store float %r, float addrspace(1)* %out
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ret void
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}
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; Due to broken cost heuristic, this is not if converted like
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; test_vccnz_ifcvt_triangle_constant_load even though it should be.
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; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle_argload:
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; GCN: v_cndmask_b32
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define amdgpu_kernel void @test_vccnz_ifcvt_triangle_argload(float addrspace(1)* %out, float %v) #0 {
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entry:
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%cc = fcmp oeq float %v, 1.000000e+00
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br i1 %cc, label %if, label %endif
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if:
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%u = fadd float %v, %v
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br label %endif
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endif:
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%r = phi float [ %v, %entry ], [ %u, %if ]
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store float %r, float addrspace(1)* %out
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ret void
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}
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; Scalar branch and scalar inputs
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; GCN-LABEL: {{^}}test_scc1_sgpr_ifcvt_triangle:
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; GCN: s_load_dword [[VAL:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x0
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; GCN: s_add_i32 [[ADD:s[0-9]+]], [[VAL]], [[VAL]]
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; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 1
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; GCN-NEXT: s_cselect_b32 [[SELECT:s[0-9]+]], [[ADD]], [[VAL]]
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define amdgpu_kernel void @test_scc1_sgpr_ifcvt_triangle(i32 addrspace(2)* %in, i32 %cond) #0 {
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entry:
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%v = load i32, i32 addrspace(2)* %in
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%cc = icmp eq i32 %cond, 1
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br i1 %cc, label %if, label %endif
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if:
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%u = add i32 %v, %v
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br label %endif
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endif:
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%r = phi i32 [ %v, %entry ], [ %u, %if ]
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call void asm sideeffect "; reg use $0", "s"(i32 %r) #0
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ret void
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}
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; FIXME: Should be able to use VALU compare and select
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; Scalar branch but VGPR select operands
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; GCN-LABEL: {{^}}test_scc1_vgpr_ifcvt_triangle:
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; GCN: s_cmp_lg_u32
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; GCN: s_cbranch_scc1 [[ENDIF:BB[0-9]+_[0-9]+]]
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; GCN: v_add_f32_e32
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; GCN: [[ENDIF]]:
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; GCN: buffer_store_dword
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define amdgpu_kernel void @test_scc1_vgpr_ifcvt_triangle(float addrspace(1)* %out, float addrspace(1)* %in, i32 %cond) #0 {
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entry:
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%v = load float, float addrspace(1)* %in
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%cc = icmp eq i32 %cond, 1
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br i1 %cc, label %if, label %endif
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if:
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%u = fadd float %v, %v
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br label %endif
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endif:
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%r = phi float [ %v, %entry ], [ %u, %if ]
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store float %r, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}test_scc1_sgpr_ifcvt_triangle64:
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; GCN: s_add_u32
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; GCN: s_addc_u32
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; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 1
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; GCN-NEXT: s_cselect_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @test_scc1_sgpr_ifcvt_triangle64(i64 addrspace(2)* %in, i32 %cond) #0 {
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entry:
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%v = load i64, i64 addrspace(2)* %in
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%cc = icmp eq i32 %cond, 1
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br i1 %cc, label %if, label %endif
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if:
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%u = add i64 %v, %v
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br label %endif
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endif:
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%r = phi i64 [ %v, %entry ], [ %u, %if ]
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call void asm sideeffect "; reg use $0", "s"(i64 %r) #0
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ret void
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}
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; TODO: Can do s_cselect_b64; s_cselect_b32
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; GCN-LABEL: {{^}}test_scc1_sgpr_ifcvt_triangle96:
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 1
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; GCN-NEXT: s_cselect_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}
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; GCN-NEXT: s_cselect_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @test_scc1_sgpr_ifcvt_triangle96(<3 x i32> addrspace(2)* %in, i32 %cond) #0 {
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entry:
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%v = load <3 x i32>, <3 x i32> addrspace(2)* %in
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%cc = icmp eq i32 %cond, 1
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br i1 %cc, label %if, label %endif
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if:
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%u = add <3 x i32> %v, %v
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br label %endif
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endif:
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%r = phi <3 x i32> [ %v, %entry ], [ %u, %if ]
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%r.ext = shufflevector <3 x i32> %r, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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call void asm sideeffect "; reg use $0", "s"(<4 x i32> %r.ext) #0
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ret void
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}
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; GCN-LABEL: {{^}}test_scc1_sgpr_ifcvt_triangle128:
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_add_i32
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; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 1
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; GCN-NEXT: s_cselect_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}
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; GCN-NEXT: s_cselect_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @test_scc1_sgpr_ifcvt_triangle128(<4 x i32> addrspace(2)* %in, i32 %cond) #0 {
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entry:
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%v = load <4 x i32>, <4 x i32> addrspace(2)* %in
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%cc = icmp eq i32 %cond, 1
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br i1 %cc, label %if, label %endif
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if:
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%u = add <4 x i32> %v, %v
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br label %endif
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endif:
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%r = phi <4 x i32> [ %v, %entry ], [ %u, %if ]
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call void asm sideeffect "; reg use $0", "s"(<4 x i32> %r) #0
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ret void
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}
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; GCN-LABEL: {{^}}uniform_if_swap_br_targets_scc_constant_select:
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; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 0
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; GCN: s_cselect_b32 s{{[0-9]+}}, 1, 0{{$}}
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define amdgpu_kernel void @uniform_if_swap_br_targets_scc_constant_select(i32 %cond, i32 addrspace(1)* %out) {
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entry:
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%cmp0 = icmp eq i32 %cond, 0
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br i1 %cmp0, label %else, label %if
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if:
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br label %done
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else:
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br label %done
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done:
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%value = phi i32 [0, %if], [1, %else]
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store i32 %value, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}ifcvt_undef_scc:
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; GCN: {{^}}; BB#0:
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; GCN-NEXT: s_load_dwordx2
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; GCN-NEXT: s_cselect_b32 s{{[0-9]+}}, 1, 0
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define amdgpu_kernel void @ifcvt_undef_scc(i32 %cond, i32 addrspace(1)* %out) {
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entry:
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br i1 undef, label %else, label %if
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if:
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br label %done
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else:
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br label %done
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done:
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%value = phi i32 [0, %if], [1, %else]
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store i32 %value, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle256:
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; GCN: v_cmp_neq_f32
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; GCN: s_cbranch_vccnz [[ENDIF:BB[0-9]+_[0-9]+]]
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; GCN: v_add_i32
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; GCN: v_add_i32
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; GCN: [[ENDIF]]:
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; GCN: buffer_store_dword
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define amdgpu_kernel void @test_vccnz_ifcvt_triangle256(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(1)* %in, float %cnd) #0 {
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entry:
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%v = load <8 x i32>, <8 x i32> addrspace(1)* %in
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%cc = fcmp oeq float %cnd, 1.000000e+00
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br i1 %cc, label %if, label %endif
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if:
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%u = add <8 x i32> %v, %v
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br label %endif
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endif:
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%r = phi <8 x i32> [ %v, %entry ], [ %u, %if ]
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store <8 x i32> %r, <8 x i32> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle512:
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; GCN: v_cmp_neq_f32
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; GCN: s_cbranch_vccnz [[ENDIF:BB[0-9]+_[0-9]+]]
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; GCN: v_add_i32
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; GCN: v_add_i32
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; GCN: [[ENDIF]]:
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; GCN: buffer_store_dword
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define amdgpu_kernel void @test_vccnz_ifcvt_triangle512(<16 x i32> addrspace(1)* %out, <16 x i32> addrspace(1)* %in, float %cnd) #0 {
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entry:
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%v = load <16 x i32>, <16 x i32> addrspace(1)* %in
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%cc = fcmp oeq float %cnd, 1.000000e+00
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br i1 %cc, label %if, label %endif
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if:
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%u = add <16 x i32> %v, %v
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br label %endif
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endif:
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%r = phi <16 x i32> [ %v, %entry ], [ %u, %if ]
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store <16 x i32> %r, <16 x i32> addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind }
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