llvm-project/llvm/test/CodeGen
Florian Hahn f63a5e91db [AArch64] Tie source and destination operands for AESMC/AESIMC.
Summary:
Most CPUs implementing AES fusion require instruction pairs of the form
    AESE Vn, _
    AESMC Vn, Vn
and
    AESD Vn, _
    AESIMC Vn, Vn

The constraint is added to AES(I)MC instructions which use the result of
an AES(E|D) instruction by using AES(I)MCTrr pseudo instructions, which
constraint source and destination registers to be the same.

A nice side effect of this change is that now all possible pairs are
scheduled back-to-back on the exynos-m1 for the misched-fusion-aes.ll
test case.

I had to update aes_load_store. The version I added initially was very
reduced and with the new constraint, AESE/AESMC could not be scheduled
back-to-back. I updated the test to be more realistic and still expose
the same scheduling problem as the initial test case.

Reviewers: t.p.northover, rengolin, evandro, kristof.beyls, silviu.baranga

Reviewed By: t.p.northover, evandro

Subscribers: aemerson, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D35299

llvm-svn: 309495
2017-07-29 20:35:28 +00:00
..
AArch64 [AArch64] Tie source and destination operands for AESMC/AESIMC. 2017-07-29 20:35:28 +00:00
AMDGPU AMDGPU: Make areMemAccessesTriviallyDisjoint more aware of segment flat 2017-07-29 01:26:21 +00:00
ARM Remove the obsolete offset parameter from @llvm.dbg.value 2017-07-28 20:21:02 +00:00
AVR [AVR] Remove the instrumentation pass 2017-07-23 23:39:11 +00:00
BPF [DAG] Fix typo preventing some stores merges to truncated stores. 2017-07-23 02:06:28 +00:00
Generic [AVR] Add/remove XFAILs to get the backend passing Generic CodeGen tests 2017-07-16 23:33:50 +00:00
Hexagon [Hexagon] Recognize C4_cmpneqi, C4_cmpltei and C4_cmplteui in NewValueJump 2017-07-24 19:35:48 +00:00
Inputs
Lanai CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
MIR AMDGPU: Implement memory model 2017-07-21 21:19:23 +00:00
MSP430 [DAG] Improve Aliasing of operations to static alloca 2017-07-18 20:06:24 +00:00
Mips Fix endianness bug in DAGCombiner::visitTRUNCATE and visitEXTRACT_VECTOR_ELT 2017-07-25 09:40:35 +00:00
NVPTX [NVPTX] Add lowering of i128 params. 2017-07-20 21:16:03 +00:00
Nios2 [Nios2] Target registration 2017-05-29 09:48:30 +00:00
PowerPC [PowerPC] enable optimizeCompareInstr for branch with static branch hint 2017-07-27 08:14:48 +00:00
SPARC [SPARC] Clean up the support for disabling fsmuld and fmuls instructions. 2017-07-20 20:09:11 +00:00
SystemZ [SystemZ] test update 2017-07-21 13:14:17 +00:00
Thumb [ARM] Allow rematerialization of ARM Thumb literal pool loads 2017-07-14 08:23:56 +00:00
Thumb2 [ARM] Adjust ifcvt heuristic for the diamond ifcvt case 2017-07-12 13:23:10 +00:00
WebAssembly Revert r308273 to reinstate part of r308100. 2017-07-19 04:15:30 +00:00
WinEH
X86 [SelectionDAG][X86] CombineBT - more aggressively determine demanded bits 2017-07-29 14:50:25 +00:00
XCore [DAG] Improve Aliasing of operations to static alloca 2017-07-18 20:06:24 +00:00