forked from OSchip/llvm-project
26 lines
920 B
Plaintext
26 lines
920 B
Plaintext
Date: Sun, 8 Jul 2001 10:02:20 -0500
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From: Vikram S. Adve <vadve@cs.uiuc.edu>
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To: vadve@cs.uiuc.edu, Ruchira Sasanka <sasanka@students.uiuc.edu>
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Cc: Chris Lattner <lattner@cs.uiuc.edu>
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Subject: RE: machine instruction operands
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I got interrupted and forgot to explain the example. In that case:
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reg will be the 3rd operand of MUL and it will be of type
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MO_MInstrVirtualReg. The field MachineInstr* minstr will point to the
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instruction that computes reg.
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numElements will be an immediate constant, not a register.
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%sp will be operand 1 of ADD and it will be of type MO_MachineReg. The
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field regNum identifies the register.
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numElements will be operand 2 of ADD and it will be of type
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MO_VMVirtualReg. The field Value* value identifies the value.
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ptr will be operand 3 of ADD will also be %sp, i.e., of
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type MO_MachineReg. regNum identifies the register.
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--Vikram
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