forked from OSchip/llvm-project
e72fe654b7
This enables fshl to be matched earlier on X86 %6 = lshr i32 %3, 1 %7 = select i1 %4, i32 -2147483648, i32 0 %8 = or i32 %6, %7 X86 uses i8 for shift amounts. SelectionDAGBuilder creates the ISD::SRL with an i8 shift type. DAGCombiner turns the select into an ISD::SHL. Prior to this patch it would use i32 for the shift amount. fshl matching failed because the shift amounts have different types. LegalizeDAG fixes the ISD::SHL shift amount to i8. This allowed fshl matching to succeed. With this patch, the ISD::SHL will be created with an i8 shift amount. This allows the fshl to match immediately. No test case beause we still end up with a fshl either way. |
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utils | ||
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LICENSE.TXT | ||
README.txt | ||
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configure | ||
llvm.spec.in |
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