forked from OSchip/llvm-project
204 lines
6.7 KiB
C++
204 lines
6.7 KiB
C++
//===-- MipsBaseInfo.h - Top level definitions for MIPS MC --- --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains small standalone helper functions and enum definitions for
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// the Mips target useful for the compiler back-end and the MC libraries.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MIPSBASEINFO_H
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#define MIPSBASEINFO_H
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#include "MipsMCTargetDesc.h"
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#include "llvm/Support/DataTypes.h"
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#include "llvm/Support/ErrorHandling.h"
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namespace llvm {
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/// MipsII - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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///
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namespace MipsII {
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/// Target Operand Flag enum.
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enum TOF {
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//===------------------------------------------------------------------===//
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// Mips Specific MachineOperand flags.
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MO_NO_FLAG,
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/// MO_GOT16 - Represents the offset into the global offset table at which
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/// the address the relocation entry symbol resides during execution.
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MO_GOT16,
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MO_GOT,
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/// MO_GOT_CALL - Represents the offset into the global offset table at
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/// which the address of a call site relocation entry symbol resides
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/// during execution. This is different from the above since this flag
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/// can only be present in call instructions.
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MO_GOT_CALL,
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/// MO_GPREL - Represents the offset from the current gp value to be used
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/// for the relocatable object file being produced.
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MO_GPREL,
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/// MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol
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/// address.
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MO_ABS_HI,
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MO_ABS_LO,
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/// MO_TLSGD - Represents the offset into the global offset table at which
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// the module ID and TSL block offset reside during execution (General
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// Dynamic TLS).
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MO_TLSGD,
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/// MO_TLSLDM - Represents the offset into the global offset table at which
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// the module ID and TSL block offset reside during execution (Local
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// Dynamic TLS).
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MO_TLSLDM,
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MO_DTPREL_HI,
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MO_DTPREL_LO,
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/// MO_GOTTPREL - Represents the offset from the thread pointer (Initial
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// Exec TLS).
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MO_GOTTPREL,
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/// MO_TPREL_HI/LO - Represents the hi and low part of the offset from
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// the thread pointer (Local Exec TLS).
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MO_TPREL_HI,
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MO_TPREL_LO,
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// N32/64 Flags.
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MO_GPOFF_HI,
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MO_GPOFF_LO,
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MO_GOT_DISP,
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MO_GOT_PAGE,
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MO_GOT_OFST
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};
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enum {
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//===------------------------------------------------------------------===//
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// Instruction encodings. These are the standard/most common forms for
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// Mips instructions.
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//
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// Pseudo - This represents an instruction that is a pseudo instruction
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// or one that has not been implemented yet. It is illegal to code generate
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// it, but tolerated for intermediate implementation stages.
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Pseudo = 0,
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/// FrmR - This form is for instructions of the format R.
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FrmR = 1,
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/// FrmI - This form is for instructions of the format I.
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FrmI = 2,
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/// FrmJ - This form is for instructions of the format J.
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FrmJ = 3,
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/// FrmFR - This form is for instructions of the format FR.
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FrmFR = 4,
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/// FrmFI - This form is for instructions of the format FI.
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FrmFI = 5,
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/// FrmOther - This form is for instructions that have no specific format.
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FrmOther = 6,
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FormMask = 15
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};
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}
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/// getMipsRegisterNumbering - Given the enum value for some register,
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/// return the number that it corresponds to.
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inline static unsigned getMipsRegisterNumbering(unsigned RegEnum)
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{
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switch (RegEnum) {
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case Mips::ZERO: case Mips::ZERO_64: case Mips::F0: case Mips::D0_64:
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case Mips::D0:
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return 0;
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case Mips::AT: case Mips::AT_64: case Mips::F1: case Mips::D1_64:
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return 1;
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case Mips::V0: case Mips::V0_64: case Mips::F2: case Mips::D2_64:
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case Mips::D1:
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return 2;
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case Mips::V1: case Mips::V1_64: case Mips::F3: case Mips::D3_64:
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return 3;
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case Mips::A0: case Mips::A0_64: case Mips::F4: case Mips::D4_64:
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case Mips::D2:
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return 4;
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case Mips::A1: case Mips::A1_64: case Mips::F5: case Mips::D5_64:
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return 5;
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case Mips::A2: case Mips::A2_64: case Mips::F6: case Mips::D6_64:
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case Mips::D3:
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return 6;
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case Mips::A3: case Mips::A3_64: case Mips::F7: case Mips::D7_64:
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return 7;
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case Mips::T0: case Mips::T0_64: case Mips::F8: case Mips::D8_64:
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case Mips::D4:
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return 8;
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case Mips::T1: case Mips::T1_64: case Mips::F9: case Mips::D9_64:
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return 9;
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case Mips::T2: case Mips::T2_64: case Mips::F10: case Mips::D10_64:
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case Mips::D5:
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return 10;
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case Mips::T3: case Mips::T3_64: case Mips::F11: case Mips::D11_64:
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return 11;
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case Mips::T4: case Mips::T4_64: case Mips::F12: case Mips::D12_64:
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case Mips::D6:
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return 12;
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case Mips::T5: case Mips::T5_64: case Mips::F13: case Mips::D13_64:
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return 13;
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case Mips::T6: case Mips::T6_64: case Mips::F14: case Mips::D14_64:
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case Mips::D7:
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return 14;
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case Mips::T7: case Mips::T7_64: case Mips::F15: case Mips::D15_64:
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return 15;
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case Mips::S0: case Mips::S0_64: case Mips::F16: case Mips::D16_64:
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case Mips::D8:
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return 16;
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case Mips::S1: case Mips::S1_64: case Mips::F17: case Mips::D17_64:
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return 17;
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case Mips::S2: case Mips::S2_64: case Mips::F18: case Mips::D18_64:
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case Mips::D9:
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return 18;
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case Mips::S3: case Mips::S3_64: case Mips::F19: case Mips::D19_64:
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return 19;
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case Mips::S4: case Mips::S4_64: case Mips::F20: case Mips::D20_64:
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case Mips::D10:
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return 20;
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case Mips::S5: case Mips::S5_64: case Mips::F21: case Mips::D21_64:
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return 21;
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case Mips::S6: case Mips::S6_64: case Mips::F22: case Mips::D22_64:
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case Mips::D11:
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return 22;
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case Mips::S7: case Mips::S7_64: case Mips::F23: case Mips::D23_64:
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return 23;
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case Mips::T8: case Mips::T8_64: case Mips::F24: case Mips::D24_64:
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case Mips::D12:
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return 24;
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case Mips::T9: case Mips::T9_64: case Mips::F25: case Mips::D25_64:
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return 25;
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case Mips::K0: case Mips::K0_64: case Mips::F26: case Mips::D26_64:
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case Mips::D13:
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return 26;
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case Mips::K1: case Mips::K1_64: case Mips::F27: case Mips::D27_64:
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return 27;
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case Mips::GP: case Mips::GP_64: case Mips::F28: case Mips::D28_64:
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case Mips::D14:
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return 28;
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case Mips::SP: case Mips::SP_64: case Mips::F29: case Mips::D29_64:
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case Mips::HWR29:
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return 29;
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case Mips::FP: case Mips::FP_64: case Mips::F30: case Mips::D30_64:
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case Mips::D15:
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return 30;
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case Mips::RA: case Mips::RA_64: case Mips::F31: case Mips::D31_64:
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return 31;
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default: llvm_unreachable("Unknown register number!");
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}
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}
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}
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#endif
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