| .. |
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AsmParser
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[AMDGPU][MC] Improved diagnostics for instructions with missing features
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2020-10-07 16:31:29 +03:00 |
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Disassembler
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[AMDGPU] Support disassembly for AMDGPU kernel descriptors
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2020-10-07 20:39:43 +05:30 |
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MCTargetDesc
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[AMDGPU] Emit correct kernel descriptor on big-endian hosts
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2020-10-06 17:29:38 +00:00 |
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TargetInfo
|
…
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Utils
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[AMDGPU] Create isGFX9Plus utility function
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2020-10-06 10:18:43 -07:00 |
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AMDGPU.h
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AMDGPU: Remove SIFixupVectorISel pass
|
2020-08-15 12:11:51 -04:00 |
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AMDGPU.td
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[AMDGPU] Implement hardware bug workaround for image instructions
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2020-10-07 07:39:52 -04:00 |
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AMDGPUAliasAnalysis.cpp
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[NFC] Remove unused GetUnderlyingObject paramenter
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2020-07-31 02:10:03 -07:00 |
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AMDGPUAliasAnalysis.h
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Remove orphan AMDGPUAAResult::Aliases and AMDGPUAAResult::PathAliases declarations. NFC.
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2020-06-25 16:00:44 +01:00 |
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AMDGPUAlwaysInlinePass.cpp
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AMDGPU: Hack out noinline on functions using LDS globals
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2020-04-02 14:12:07 -04:00 |
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AMDGPUAnnotateKernelFeatures.cpp
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AMDGPU: Annotate functions that have stack objects
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2020-05-19 18:51:00 -04:00 |
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AMDGPUAnnotateUniformValues.cpp
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AMDGPU: Put inexpensive ops first in AMDGPUAnnotateUniformValues::visitLoadInst
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2020-07-30 14:37:06 -07:00 |
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AMDGPUArgumentUsageInfo.cpp
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AMDGPU/GlobalISel: Add types to special inputs
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2020-07-06 17:00:55 -04:00 |
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AMDGPUArgumentUsageInfo.h
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AMDGPU: Use MCRegister for preloaded arguments
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2020-07-20 13:34:28 -04:00 |
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AMDGPUAsmPrinter.cpp
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[AMDGPU][CODEGEN] Added support of new inline assembler constraints
|
2020-07-02 17:20:15 +03:00 |
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AMDGPUAsmPrinter.h
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[AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI*
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2020-02-13 22:08:55 -08:00 |
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AMDGPUAtomicOptimizer.cpp
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[AMDGPU] Do not generate mul with 1 in AMDGPU Atomic Optimizer
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2020-09-30 11:09:18 +02:00 |
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AMDGPUCallLowering.cpp
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AMDGPU/GlobalISel: Stop using G_EXTRACT in argument lowering
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2020-08-06 09:55:35 -04:00 |
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AMDGPUCallLowering.h
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AMDGPU/GlobalISel: Mark GlobalISel classes as final
|
2020-07-28 11:42:17 -04:00 |
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AMDGPUCallingConv.td
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[AMDGPU] Introduce more scratch registers in the ABI.
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2020-05-05 23:02:58 +05:30 |
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AMDGPUCodeGenPrepare.cpp
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SelectionDAG.h - remove unnecessary FunctionLoweringInfo.h include. NFCI.
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2020-09-03 18:33:25 +01:00 |
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AMDGPUCombine.td
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[GlobalISel] Rewrite the elide-br-by-swapping-icmp-ops combine to do less.
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2020-09-09 13:08:16 -07:00 |
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AMDGPUExportClustering.cpp
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[AMDGPU] Strengthen export cluster ordering
|
2020-05-13 23:07:37 +09:00 |
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AMDGPUExportClustering.h
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[AMDGPU] Cluster shader exports
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2020-05-07 19:05:38 +09:00 |
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AMDGPUFeatures.td
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AMDGPU: Change internal tracking of wave size
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2020-06-01 17:55:08 -04:00 |
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AMDGPUFixFunctionBitcasts.cpp
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AMDGPU.h - reduce TargetMachine.h include. NFC.
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2020-05-24 15:27:41 +01:00 |
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AMDGPUFrameLowering.cpp
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…
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AMDGPUFrameLowering.h
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…
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AMDGPUGISel.td
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[AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores
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2020-08-21 12:26:31 +02:00 |
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AMDGPUGenRegisterBankInfo.def
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AMDGPU/GlobalISel: Fix missing 256-bit AGPR mapping
|
2020-08-17 09:53:26 -04:00 |
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AMDGPUGlobalISelUtils.cpp
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AMDGPU/GlobalISel: Select G_SHUFFLE_VECTOR
|
2020-02-21 13:35:40 -05:00 |
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AMDGPUGlobalISelUtils.h
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[AMDGPU] Use tablegen for argument indices
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2020-10-05 11:50:52 +02:00 |
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AMDGPUHSAMetadataStreamer.cpp
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AMDGPU: Start interpreting byref on kernel arguments
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2020-07-21 18:11:22 -04:00 |
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AMDGPUHSAMetadataStreamer.h
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AMDGPU: Start interpreting byref on kernel arguments
|
2020-07-21 18:11:22 -04:00 |
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AMDGPUISelDAGToDAG.cpp
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[AMDGPU] Simplify getNumFlatOffsetBits. NFC.
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2020-10-01 15:24:09 +01:00 |
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AMDGPUISelLowering.cpp
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[AMDGPU] Reformat AMDGPUTargetLowering::isSDNodeAlwaysUniform. NFC.
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2020-09-28 16:24:16 +01:00 |
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AMDGPUISelLowering.h
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[SelectionDAG] Always intersect SDNode flags during getNode() node memoization.
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2020-09-05 10:30:38 +02:00 |
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AMDGPUInline.cpp
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[NFC] Remove unused GetUnderlyingObject paramenter
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2020-07-31 02:10:03 -07:00 |
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AMDGPUInstCombineIntrinsic.cpp
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Internalize functions from various tools. NFC
|
2020-09-26 15:57:13 -07:00 |
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AMDGPUInstrInfo.cpp
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[AMDGPU] Remove AMDGPURegisterInfo
|
2020-02-11 11:13:38 -08:00 |
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AMDGPUInstrInfo.h
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[AMDGPU] Use tablegen for argument indices
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2020-10-05 11:50:52 +02:00 |
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AMDGPUInstrInfo.td
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AMDGPU: Remove intermediate DAG node for trig_preop intrinsic
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2020-06-16 21:06:25 -04:00 |
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AMDGPUInstructionSelector.cpp
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[AMDGPU] Implement hardware bug workaround for image instructions
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2020-10-07 07:39:52 -04:00 |
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AMDGPUInstructionSelector.h
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[AMDGPU] global-isel support for RT
|
2020-09-24 10:29:45 -07:00 |
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AMDGPUInstructions.td
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[AMDGPU] Split R600 and GCN bfe patterns
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2020-10-05 09:55:10 +01:00 |
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AMDGPULegalizerInfo.cpp
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[AMDGPU] Implement hardware bug workaround for image instructions
|
2020-10-07 07:39:52 -04:00 |
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AMDGPULegalizerInfo.h
|
[AMDGPU] Implement hardware bug workaround for image instructions
|
2020-10-07 07:39:52 -04:00 |
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AMDGPULibCalls.cpp
|
Use llvm::is_contained where appropriate (NFC)
|
2020-07-27 10:20:44 -07:00 |
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AMDGPULibFunc.cpp
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[SVE] Eliminate calls to default-false VectorType::get() from AMDGPU
|
2020-05-29 17:54:17 -07:00 |
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AMDGPULibFunc.h
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AMDGPULibFunc - fix include order. NFC.
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2020-05-24 13:25:59 +01:00 |
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AMDGPULowerIntrinsics.cpp
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AMDGPU: Use caller subtarget, not intrinsic declaration
|
2020-08-27 16:42:09 -04:00 |
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AMDGPULowerKernelArguments.cpp
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AMDGPU: Start interpreting byref on kernel arguments
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2020-07-21 18:11:22 -04:00 |
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AMDGPULowerKernelAttributes.cpp
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…
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AMDGPUMCInstLower.cpp
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[AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI*
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2020-02-13 22:08:55 -08:00 |
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AMDGPUMachineCFGStructurizer.cpp
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[AMDGPU] Apply llvm-prefer-register-over-unsigned from clang-tidy
|
2020-08-21 10:14:35 +01:00 |
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AMDGPUMachineFunction.cpp
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[amdgpu] Add codegen support for HIP dynamic shared memory.
|
2020-08-20 21:29:18 -04:00 |
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AMDGPUMachineFunction.h
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[amdgpu] Add codegen support for HIP dynamic shared memory.
|
2020-08-20 21:29:18 -04:00 |
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AMDGPUMachineModuleInfo.cpp
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…
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AMDGPUMachineModuleInfo.h
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…
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AMDGPUMacroFusion.cpp
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[AMDGPU] Extend macro fusion for ADDC and SUBB to SUBBREV
|
2020-03-11 17:59:21 +00:00 |
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AMDGPUMacroFusion.h
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…
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AMDGPUOpenCLEnqueuedBlockLowering.cpp
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Avoid SmallString.h include in MD5.h, NFC
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2020-02-26 09:10:24 -08:00 |
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AMDGPUPTNote.h
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…
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AMDGPUPerfHintAnalysis.cpp
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AMDGPU.h - reduce TargetMachine.h include. NFC.
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2020-05-24 15:27:41 +01:00 |
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AMDGPUPerfHintAnalysis.h
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…
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AMDGPUPostLegalizerCombiner.cpp
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AMDGPU/GlobalISel: Fix using post-legal combiner without LegalizerInfo
|
2020-08-17 09:19:22 -04:00 |
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AMDGPUPreLegalizerCombiner.cpp
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AMDGPU/GlobalISel: Mark GlobalISel classes as final
|
2020-07-28 11:42:17 -04:00 |
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AMDGPUPrintfRuntimeBinding.cpp
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AMDGPUPrintfRuntimeBinding.cpp - drop unnecessary casts/dyn_casts. NFCI.
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2020-09-15 14:49:04 +01:00 |
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AMDGPUPromoteAlloca.cpp
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[NFC] Remove unused GetUnderlyingObject paramenter
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2020-07-31 02:10:03 -07:00 |
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AMDGPUPropagateAttributes.cpp
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[AMDGPU] Propagate amdgpu-waves-per-eu to callees
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2020-03-26 14:43:44 -07:00 |
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AMDGPURegBankCombiner.cpp
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AMDGPU/GlobalISel: Mark GlobalISel classes as final
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2020-07-28 11:42:17 -04:00 |
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AMDGPURegisterBankInfo.cpp
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[AMDGPU] global-isel support for RT
|
2020-09-24 10:29:45 -07:00 |
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AMDGPURegisterBankInfo.h
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AMDGPU/GlobalISel: Start trying to handle AGPR bank
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2020-08-06 12:39:50 -04:00 |
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AMDGPURegisterBanks.td
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AMDGPU/GlobalISel: Add SReg_96 to SGPRRegBank
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2020-07-28 16:49:55 -04:00 |
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AMDGPURewriteOutArguments.cpp
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[SVE] Remove usages of VectorType::getNumElements() from AMDGPU
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2020-05-13 15:57:55 -07:00 |
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AMDGPUSearchableTables.td
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AMDGPU: Define raw/struct variants of buffer atomic fadd
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2020-08-06 13:36:19 -04:00 |
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AMDGPUSubtarget.cpp
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[AMDGPU] Implement hardware bug workaround for image instructions
|
2020-10-07 07:39:52 -04:00 |
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AMDGPUSubtarget.h
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[AMDGPU] Implement hardware bug workaround for image instructions
|
2020-10-07 07:39:52 -04:00 |
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AMDGPUTargetMachine.cpp
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[OldPM] Pass manager: run SROA after (simple) loop unrolling
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2020-10-04 11:53:50 +03:00 |
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AMDGPUTargetMachine.h
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Support addrspacecast initializers with isNoopAddrSpaceCast
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2020-07-31 10:42:43 -04:00 |
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AMDGPUTargetObjectFile.cpp
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…
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AMDGPUTargetObjectFile.h
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AMDGPUTargetObjectFile.h - remove unnecessary includes. NFC.
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2020-05-24 13:57:02 +01:00 |
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AMDGPUTargetTransformInfo.cpp
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Change LoopInfo::empty to isInnermost after D82895
|
2020-09-22 14:07:40 -07:00 |
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AMDGPUTargetTransformInfo.h
|
Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access"
|
2020-09-29 15:33:34 +02:00 |
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AMDGPUUnifyDivergentExitNodes.cpp
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Reland "[NFC] SimplifyCFGOptions: drop multi-parameter ctor, use default member-init"
|
2020-07-16 13:40:01 +03:00 |
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AMDGPUUnifyMetadata.cpp
|
Use llvm::is_contained where appropriate (NFC)
|
2020-07-27 10:20:44 -07:00 |
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AMDILCFGStructurizer.cpp
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…
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AMDKernelCodeT.h
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…
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BUFInstructions.td
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[AMDGPU] Add v3f16/v3i16 support to SDag
|
2020-09-16 17:20:27 +02:00 |
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CMakeLists.txt
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AMDGPU: Remove SIFixupVectorISel pass
|
2020-08-15 12:11:51 -04:00 |
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CaymanInstructions.td
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[AMDGPU] Fix and simplify AMDGPUTargetLowering::LowerUDIVREM
|
2020-07-08 19:14:49 +01:00 |
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DSInstructions.td
|
[AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores
|
2020-08-21 12:26:31 +02:00 |
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EvergreenInstructions.td
|
[AMDGPU] Split R600 and GCN bfe patterns
|
2020-10-05 09:55:10 +01:00 |
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FLATInstructions.td
|
[AMDGPU] Unify intrinsic ret/nortn interface
|
2020-09-15 15:26:42 -07:00 |
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GCNDPPCombine.cpp
|
AMDGPU: Rename add/sub with carry out instructions
|
2020-07-16 13:16:30 -04:00 |
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GCNHazardRecognizer.cpp
|
[AMDGPU] Enable scheduling around FP MODE-setting instructions
|
2020-09-16 16:10:47 +01:00 |
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GCNHazardRecognizer.h
|
[AMDGPU] prefer non-mfma in post-RA schedule
|
2020-07-29 12:17:50 -07:00 |
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GCNILPSched.cpp
|
…
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GCNIterativeScheduler.cpp
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[AMDGPU] Add file headers for few files where it is missing.
|
2020-01-31 02:06:41 +05:30 |
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GCNIterativeScheduler.h
|
[AMDGPU] Add file headers for few files where it is missing.
|
2020-01-31 02:06:41 +05:30 |
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GCNMinRegStrategy.cpp
|
Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit"
|
2020-09-21 13:33:05 +02:00 |
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GCNNSAReassign.cpp
|
[NFC][Regalloc] accessors for 'reg' and 'weight'
|
2020-09-16 08:28:57 -07:00 |
|
GCNProcessors.td
|
[AMDGPU] gfx1031 target
|
2020-08-05 12:36:26 -07:00 |
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GCNRegBankReassign.cpp
|
[NFC][Regalloc] accessors for 'reg' and 'weight'
|
2020-09-16 08:28:57 -07:00 |
|
GCNRegPressure.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
GCNRegPressure.h
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
GCNSchedStrategy.cpp
|
[AMDGPU] Fix not rescheduling without clustering
|
2020-08-07 11:15:58 -07:00 |
|
GCNSchedStrategy.h
|
…
|
|
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InstCombineTables.td
|
[InstCombine] Move target-specific inst combining
|
2020-07-22 15:59:49 +02:00 |
|
LLVMBuild.txt
|
…
|
|
|
MIMGInstructions.td
|
[AMDGPU] Use tablegen for argument indices
|
2020-10-05 11:50:52 +02:00 |
|
R600.td
|
…
|
|
|
R600AsmPrinter.cpp
|
[MC] Add MCStreamer::emitInt{8,16,32,64}
|
2020-02-29 09:40:21 -08:00 |
|
R600AsmPrinter.h
|
[AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI*
|
2020-02-13 22:08:55 -08:00 |
|
R600ClauseMergePass.cpp
|
…
|
|
|
R600ControlFlowFinalizer.cpp
|
[AMDGPU] Make use of divideCeil. NFC.
|
2020-03-26 16:11:35 +00:00 |
|
R600Defines.h
|
…
|
|
|
R600EmitClauseMarkers.cpp
|
…
|
|
|
R600ExpandSpecialInstrs.cpp
|
[AMDGPU] Split R600 and GCN subregs
|
2020-02-10 08:29:56 -08:00 |
|
R600FrameLowering.cpp
|
CodeGen: Use Register in TargetFrameLowering
|
2020-04-07 17:07:44 -04:00 |
|
R600FrameLowering.h
|
CodeGen: Use Register in TargetFrameLowering
|
2020-04-07 17:07:44 -04:00 |
|
R600ISelLowering.cpp
|
[AMDGPU] Use cast instead of dyn_cast
|
2020-09-24 15:20:49 +01:00 |
|
R600ISelLowering.h
|
…
|
|
|
R600InstrFormats.td
|
…
|
|
|
R600InstrInfo.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
R600InstrInfo.h
|
…
|
|
|
R600Instructions.td
|
[NFC] Remove unused GetUnderlyingObject paramenter
|
2020-07-31 02:10:03 -07:00 |
|
R600MachineFunctionInfo.cpp
|
…
|
|
|
R600MachineFunctionInfo.h
|
…
|
|
|
R600MachineScheduler.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
R600MachineScheduler.h
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
R600OpenCLImageTypeLoweringPass.cpp
|
…
|
|
|
R600OptimizeVectorRegisters.cpp
|
AMDGPU: Use Register
|
2020-06-30 12:13:08 -04:00 |
|
R600Packetizer.cpp
|
…
|
|
|
R600Processors.td
|
…
|
|
|
R600RegisterInfo.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
R600RegisterInfo.h
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
R600RegisterInfo.td
|
[TBLGEN] Allow to override RC weight
|
2020-02-14 15:49:52 -08:00 |
|
R600Schedule.td
|
…
|
|
|
R700Instructions.td
|
…
|
|
|
SIAddIMGInit.cpp
|
[AMDGPU] gfx1030 RT support
|
2020-09-16 11:40:58 -07:00 |
|
SIAnnotateControlFlow.cpp
|
AMDGPU: Fix extra type mangling on llvm.amdgcn.if.break
|
2020-02-03 07:02:05 -08:00 |
|
SIDefines.h
|
[AMDGPU][MC] Corrected parser to avoid generation of excessive error messages
|
2020-09-02 19:42:18 +03:00 |
|
SIFixSGPRCopies.cpp
|
[AMDGPU] Fix merging m0 inits
|
2020-09-23 09:13:43 +02:00 |
|
SIFixVGPRCopies.cpp
|
…
|
|
|
SIFoldOperands.cpp
|
[AMDGPU] More codegen patterns for v2i16/v2f16 build_vector
|
2020-09-22 10:41:38 +01:00 |
|
SIFormMemoryClauses.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
SIFrameLowering.cpp
|
[AMDGPU] Remove the dead spill slots while spilling FP/BP to memory
|
2020-09-06 07:04:25 +05:30 |
|
SIFrameLowering.h
|
AMDGPU: Correct prolog SP initialization logic
|
2020-08-05 15:47:53 -04:00 |
|
SIISelLowering.cpp
|
[AMDGPU] Implement hardware bug workaround for image instructions
|
2020-10-07 07:39:52 -04:00 |
|
SIISelLowering.h
|
[AMDGPU] Implement hardware bug workaround for image instructions
|
2020-10-07 07:39:52 -04:00 |
|
SIInsertHardClauses.cpp
|
[AMDGPU/MemOpsCluster] Let mem ops clustering logic also consider number of clustered bytes
|
2020-06-01 22:52:34 +05:30 |
|
SIInsertSkips.cpp
|
[AMDGPU] SIInsertSkips: Refactor early exit block creation
|
2020-10-06 09:44:55 +09:00 |
|
SIInsertWaitcnts.cpp
|
Revert "[AMDGPU] Insert waitcnt after returning from call"
|
2020-09-23 17:16:39 +02:00 |
|
SIInstrFormats.td
|
AMDGPU: Start adding MODE register uses to instructions
|
2020-05-27 14:47:00 -04:00 |
|
SIInstrInfo.cpp
|
[AMDGPU] Remove SIInstrInfo::calculateLDSSpillAddress
|
2020-10-06 18:45:22 +02:00 |
|
SIInstrInfo.h
|
[AMDGPU] Remove SIInstrInfo::calculateLDSSpillAddress
|
2020-10-06 18:45:22 +02:00 |
|
SIInstrInfo.td
|
[AMDGPU] Remove SIEncodingFamily.GFX10_B
|
2020-09-29 15:59:49 -07:00 |
|
SIInstructions.td
|
[AMDGPU] Make bfe patterns divergence-aware
|
2020-10-05 09:55:10 +01:00 |
|
SILoadStoreOptimizer.cpp
|
[AMDGPU] gfx1030 RT support
|
2020-09-16 11:40:58 -07:00 |
|
SILowerControlFlow.cpp
|
CodeGen: Move split block utility to MachineBasicBlock
|
2020-09-18 14:05:18 -04:00 |
|
SILowerI1Copies.cpp
|
[AMDGPU] Apply llvm-prefer-register-over-unsigned from clang-tidy
|
2020-08-21 10:14:35 +01:00 |
|
SILowerSGPRSpills.cpp
|
[AMDGPU] Scavenge temp reg for AGPR spill
|
2020-08-05 13:29:19 -07:00 |
|
SIMachineFunctionInfo.cpp
|
[amdgpu] Add codegen support for HIP dynamic shared memory.
|
2020-08-20 21:29:18 -04:00 |
|
SIMachineFunctionInfo.h
|
[amdgpu] Add codegen support for HIP dynamic shared memory.
|
2020-08-20 21:29:18 -04:00 |
|
SIMachineScheduler.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
SIMachineScheduler.h
|
Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit"
|
2020-09-21 13:33:05 +02:00 |
|
SIMemoryLegalizer.cpp
|
[AMDGPU] Make generating cache invalidating instructions optional
|
2020-07-27 09:24:11 +02:00 |
|
SIModeRegister.cpp
|
[AMDGPU] Enable scheduling around FP MODE-setting instructions
|
2020-09-16 16:10:47 +01:00 |
|
SIOptimizeExecMasking.cpp
|
AMDGPU: Don't sometimes allow instructions before lowered si_end_cf
|
2020-09-18 13:43:01 -04:00 |
|
SIOptimizeExecMaskingPreRA.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
|
2020-08-20 17:59:11 +01:00 |
|
SIPeepholeSDWA.cpp
|
[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
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2020-08-20 17:59:11 +01:00 |
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SIPostRABundler.cpp
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AMDGPU: Do not bundle inline asm
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2020-06-14 13:24:50 -04:00 |
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SIPreAllocateWWMRegs.cpp
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[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
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2020-08-20 17:59:11 +01:00 |
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SIPreEmitPeephole.cpp
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[AMDGPU] Fix missed SI_RETURN_TO_EPILOG in pre-emit peephole
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2020-08-13 21:52:41 +09:00 |
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SIProgramInfo.h
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…
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SIRegisterInfo.cpp
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AMDGPU: Clear offset register when using local stack area
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2020-09-16 12:56:40 -04:00 |
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SIRegisterInfo.h
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[NFC] Move getAll{S,V}GPR{32,128} methods to SIFrameLowering
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2020-06-17 12:08:09 -04:00 |
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SIRegisterInfo.td
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AMDGPU: Define mode register
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2020-05-23 13:24:42 -04:00 |
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SIRemoveShortExecBranches.cpp
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[AMDGPU] Don't remove short branches over kills
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2020-02-03 09:26:52 +00:00 |
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SISchedule.td
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[AMDGPU] Add XDL resource to scheduling model
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2020-09-14 13:48:54 -07:00 |
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SIShrinkInstructions.cpp
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[AMDGPU] gfx1030 RT support
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2020-09-16 11:40:58 -07:00 |
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SIWholeQuadMode.cpp
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[AMDGPU] Remove uses of Register::isPhysicalRegister/isVirtualRegister
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2020-08-20 17:59:11 +01:00 |
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SMInstructions.td
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AMDGPU: Remove mayLoad/mayStore from some side effecting intrinsics
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2020-06-18 14:12:19 -04:00 |
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SOPInstructions.td
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[AMDGPU] Allow SOP asm mnemonic to differ
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2020-10-01 16:00:04 -07:00 |
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VIInstrFormats.td
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…
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VOP1Instructions.td
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[AMDGPU] Removed s_mov_regrd and mov_fed opcodes
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2020-07-17 19:52:54 +03:00 |
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VOP2Instructions.td
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AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat
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2020-07-28 11:18:05 -04:00 |
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VOP3Instructions.td
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AMDGPU/GlobalISel/Emitter Support for predicate code that uses operands
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2020-09-14 10:39:56 +02:00 |
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VOP3PInstructions.td
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[AMDGPU] Reorganize VOP3P encoding
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2020-09-30 15:27:06 -07:00 |
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VOPCInstructions.td
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AMDGPU: Start adding MODE register uses to instructions
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2020-05-27 14:47:00 -04:00 |
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VOPInstructions.td
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[AMDGPU] Reorganize VOP3P encoding
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2020-09-30 15:27:06 -07:00 |
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