Vladimir Sukharev 5f6f60d942 [AArch64] Add v8.1a atomic instructions ... Patch by: Tom Coxon Reviewers: t.p.northover Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8501 llvm-svn: 238818		2015-06-02 10:58:41 +00:00
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AArch64	[AArch64] Add v8.1a atomic instructions	2015-06-02 10:58:41 +00:00
ARM	Don't special case undefined symbol when deciding the symbol order.	2015-05-28 21:59:34 +00:00
AsmParser	Relax these tests a bit.	2015-05-22 21:37:13 +00:00
COFF	Revise test to run llc and llvm-mc separately.	2015-05-28 21:49:50 +00:00
Disassembler	[AArch64] Add v8.1a atomic instructions	2015-06-02 10:58:41 +00:00
ELF	Don't special case undefined symbol when deciding the symbol order.	2015-05-28 21:59:34 +00:00
Hexagon	[Hexagon] Disassembling, printing, and emitting instructions a whole-bundle at a time which is the semantic unit for Hexagon. Fixing tests to use the new format. Disabling tests in the direct object emission path for a followup patch.	2015-05-29 14:44:13 +00:00
MachO	AArch64: work around ld64 bug more aggressively.	2015-05-18 22:07:20 +00:00
Markup	MC: Simple example parser for MC assembly markup.	2012-10-31 23:24:13 +00:00
Mips	[mips] [IAS] Reformat mips-expansions.s. NFC.	2015-06-02 10:34:10 +00:00
PowerPC	Add support for VSX FMA single-precision instructions to the PPC back end	2015-05-29 17:13:25 +00:00
R600	R600/SI: Add assembler support for all CI and VI VOP2 instructions	2015-05-26 15:55:52 +00:00
Sparc	Sparc: support the "set" synthetic instruction.	2015-05-18 16:43:33 +00:00
SystemZ	[SystemZ] Add z13 vector facility and MC support	2015-05-05 19:23:40 +00:00
X86	AVX-512: Implemented VFIXUPIMMSD and VFIXUPIMMSS instructions for KNL	2015-06-02 08:28:57 +00:00