forked from OSchip/llvm-project
163 lines
4.8 KiB
LLVM
163 lines
4.8 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -aarch64-neon-syntax=apple -verify-machineinstrs -o - %s | FileCheck %s
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; CHECK-LABEL: test1
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; CHECK-NOT: fmul.2s
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; CHECK: fcvtzs.2s v0, v0, #4
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; CHECK: ret
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define <2 x i32> @test1(<2 x float> %f) {
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%mul.i = fmul <2 x float> %f, <float 16.000000e+00, float 16.000000e+00>
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%vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
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ret <2 x i32> %vcvt.i
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}
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; CHECK-LABEL: test2
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; CHECK-NOT: fmul.4s
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; CHECK: fcvtzs.4s v0, v0, #3
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; CHECK: ret
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define <4 x i32> @test2(<4 x float> %f) {
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%mul.i = fmul <4 x float> %f, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>
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%vcvt.i = fptosi <4 x float> %mul.i to <4 x i32>
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ret <4 x i32> %vcvt.i
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}
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; CHECK-LABEL: test3
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; CHECK-NOT: fmul.2d
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; CHECK: fcvtzs.2d v0, v0, #5
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; CHECK: ret
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define <2 x i64> @test3(<2 x double> %d) {
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%mul.i = fmul <2 x double> %d, <double 32.000000e+00, double 32.000000e+00>
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%vcvt.i = fptosi <2 x double> %mul.i to <2 x i64>
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ret <2 x i64> %vcvt.i
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}
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; Truncate double to i32
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; CHECK-LABEL: test4
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; CHECK-NOT: fmul.2d v0, v0, #4
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; CHECK: fcvtzs.2d v0, v0
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; CHECK: xtn.2s
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; CHECK: ret
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define <2 x i32> @test4(<2 x double> %d) {
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%mul.i = fmul <2 x double> %d, <double 16.000000e+00, double 16.000000e+00>
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%vcvt.i = fptosi <2 x double> %mul.i to <2 x i32>
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ret <2 x i32> %vcvt.i
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}
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; Truncate float to i16
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; CHECK-LABEL: test5
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; CHECK-NOT: fmul.2s
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; CHECK: fcvtzs.2s v0, v0, #4
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; CHECK: ret
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define <2 x i16> @test5(<2 x float> %f) {
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%mul.i = fmul <2 x float> %f, <float 16.000000e+00, float 16.000000e+00>
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%vcvt.i = fptosi <2 x float> %mul.i to <2 x i16>
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ret <2 x i16> %vcvt.i
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}
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; Don't convert float to i64
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; CHECK-LABEL: test6
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; CHECK: fmov.2s v1, #16.00000000
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; CHECK: fmul.2s v0, v0, v1
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; CHECK: fcvtl v0.2d, v0.2s
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; CHECK: fcvtzs.2d v0, v0
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; CHECK: ret
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define <2 x i64> @test6(<2 x float> %f) {
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%mul.i = fmul <2 x float> %f, <float 16.000000e+00, float 16.000000e+00>
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%vcvt.i = fptosi <2 x float> %mul.i to <2 x i64>
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ret <2 x i64> %vcvt.i
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}
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; Check unsigned conversion.
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; CHECK-LABEL: test7
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; CHECK-NOT: fmul.2s
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; CHECK: fcvtzu.2s v0, v0, #4
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; CHECK: ret
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define <2 x i32> @test7(<2 x float> %f) {
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%mul.i = fmul <2 x float> %f, <float 16.000000e+00, float 16.000000e+00>
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%vcvt.i = fptoui <2 x float> %mul.i to <2 x i32>
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ret <2 x i32> %vcvt.i
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}
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; Test which should not fold due to non-power of 2.
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; CHECK-LABEL: test8
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; CHECK: fmov.2s v1, #17.00000000
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; CHECK: fmul.2s v0, v0, v1
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; CHECK: fcvtzu.2s v0, v0
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; CHECK: ret
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define <2 x i32> @test8(<2 x float> %f) {
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%mul.i = fmul <2 x float> %f, <float 17.000000e+00, float 17.000000e+00>
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%vcvt.i = fptoui <2 x float> %mul.i to <2 x i32>
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ret <2 x i32> %vcvt.i
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}
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; Test which should not fold due to non-matching power of 2.
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; CHECK-LABEL: test9
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; CHECK: fmul.2s v0, v0, v1
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; CHECK: fcvtzu.2s v0, v0
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; CHECK: ret
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define <2 x i32> @test9(<2 x float> %f) {
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%mul.i = fmul <2 x float> %f, <float 16.000000e+00, float 8.000000e+00>
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%vcvt.i = fptoui <2 x float> %mul.i to <2 x i32>
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ret <2 x i32> %vcvt.i
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}
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; Don't combine all undefs.
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; CHECK-LABEL: test10
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; CHECK: fmul.2s v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; CHECK: fcvtzu.2s v{{[0-9]+}}, v{{[0-9]+}}
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; CHECK: ret
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define <2 x i32> @test10(<2 x float> %f) {
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%mul.i = fmul <2 x float> %f, <float undef, float undef>
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%vcvt.i = fptoui <2 x float> %mul.i to <2 x i32>
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ret <2 x i32> %vcvt.i
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}
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; Combine if mix of undef and pow2.
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; CHECK-LABEL: test11
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; CHECK: fcvtzu.2s v0, v0, #3
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; CHECK: ret
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define <2 x i32> @test11(<2 x float> %f) {
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%mul.i = fmul <2 x float> %f, <float undef, float 8.000000e+00>
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%vcvt.i = fptoui <2 x float> %mul.i to <2 x i32>
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ret <2 x i32> %vcvt.i
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}
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; Don't combine when multiplied by 0.0.
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; CHECK-LABEL: test12
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; CHECK: fmul.2s v0, v0, v1
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; CHECK: fcvtzs.2s v0, v0
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; CHECK: ret
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define <2 x i32> @test12(<2 x float> %f) {
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%mul.i = fmul <2 x float> %f, <float 0.000000e+00, float 0.000000e+00>
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%vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
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ret <2 x i32> %vcvt.i
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}
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; Test which should not fold due to power of 2 out of range (i.e., 2^33).
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; CHECK-LABEL: test13
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; CHECK: fmul.2s v0, v0, v1
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; CHECK: fcvtzs.2s v0, v0
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; CHECK: ret
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define <2 x i32> @test13(<2 x float> %f) {
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%mul.i = fmul <2 x float> %f, <float 0x4200000000000000, float 0x4200000000000000>
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%vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
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ret <2 x i32> %vcvt.i
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}
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; Test case where const is max power of 2 (i.e., 2^32).
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; CHECK-LABEL: test14
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; CHECK: fcvtzs.2s v0, v0, #32
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; CHECK: ret
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define <2 x i32> @test14(<2 x float> %f) {
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%mul.i = fmul <2 x float> %f, <float 0x41F0000000000000, float 0x41F0000000000000>
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%vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
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ret <2 x i32> %vcvt.i
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}
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; CHECK-LABEL: test_illegal_fp_to_int:
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; CHECK: fcvtzs.4s v0, v0, #2
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define <3 x i32> @test_illegal_fp_to_int(<3 x float> %in) {
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%scale = fmul <3 x float> %in, <float 4.0, float 4.0, float 4.0>
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%val = fptosi <3 x float> %scale to <3 x i32>
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ret <3 x i32> %val
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}
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