llvm-project/llvm/test/MC
Craig Topper 49225d0915 [X86][Disassembler] Add bizarro versions of the MOVSXD instruction that sign extend from a GR32 to GR32 or GR16.
The 0x63 opcodes in 64-bit mode have a fixed source size of 32-bits, but the destination size is controlled by REX.W and the 0x66 opsize prefix. This instruction is normally used with a REX.W prefix which provides desired behavior. The other encodings are interpretted as valid by the processor, but aren't useful.

This patch makes us recognize them for the disassembler to match objdump.

llvm-svn: 343614
2018-10-02 18:16:19 +00:00
..
AArch64 [AArch64][v8.5A] Add Memory Tagging instructions 2018-10-02 10:04:39 +00:00
AMDGPU AMDGPU: Print all kernel descriptor directives (including the ones with default values) 2018-09-12 20:25:39 +00:00
ARM [ARM] Emmit data symbol for constant pool data 2018-10-02 14:55:48 +00:00
AVR [AVR] Redefine the 'SBR' instruction as an alias 2018-09-01 12:22:54 +00:00
AsmParser [debuginfo] generate debug info with asm+.file 2018-08-28 16:23:39 +00:00
BPF bpf: New disassembler testcases for 32-bit subregister support 2018-02-23 23:49:35 +00:00
COFF [codeview] Fix 32-bit x86 variable locations in realigned stack frames 2018-10-02 16:43:52 +00:00
Disassembler [X86][Disassembler] Add bizarro versions of the MOVSXD instruction that sign extend from a GR32 to GR32 or GR16. 2018-10-02 18:16:19 +00:00
ELF [lib/MC] - Set SHF_EXCLUDE flag for .dwo sections. 2018-09-22 07:36:20 +00:00
Hexagon Check for tied operands 2018-08-13 14:01:25 +00:00
Lanai
MachO [MC/Dwarf] Unclamp DWARF linetables format on Darwin. 2018-09-13 13:13:50 +00:00
Mips [mips] Fix MIPS N32 ABI triples support 2018-09-17 21:21:57 +00:00
PowerPC [MC] Avoid inlining constant symbols with variants. 2018-09-17 20:34:26 +00:00
RISCV [RISCV][MC] Improve parsing of jal/j operands 2018-09-20 08:10:35 +00:00
Sparc [Sparc] Add unimp alias 2018-09-27 12:34:53 +00:00
SystemZ [SystemZ, AsmParser] Enable the mnemonic spell corrector. 2017-07-18 09:17:00 +00:00
WebAssembly [WebAssembly] Restore slashes in SIMD conversion names 2018-10-02 01:52:21 +00:00
X86 [X86][Assembler] Allow %eip as a register in 32-bit mode for .cfi directives. 2018-09-06 02:03:14 +00:00