forked from OSchip/llvm-project
88 lines
2.9 KiB
C++
88 lines
2.9 KiB
C++
//===- PTXInstrInfo.cpp - PTX Instruction Information ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PTX implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "PTX.h"
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#include "PTXInstrInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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using namespace llvm;
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#include "PTXGenInstrInfo.inc"
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PTXInstrInfo::PTXInstrInfo(PTXTargetMachine &_TM)
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: TargetInstrInfoImpl(PTXInsts, array_lengthof(PTXInsts)),
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RI(_TM, *this), TM(_TM) {}
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static const struct map_entry {
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const TargetRegisterClass *cls;
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const int opcode;
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} map[] = {
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{ &PTX::RRegs32RegClass, PTX::MOVrr },
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{ &PTX::PredsRegClass, PTX::MOVpp }
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};
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void PTXInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DstReg, unsigned SrcReg,
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bool KillSrc) const {
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for (int i = 0, e = sizeof(map)/sizeof(map[0]); i != e; ++ i)
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if (PTX::RRegs32RegClass.contains(DstReg, SrcReg)) {
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BuildMI(MBB, I, DL,
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get(PTX::MOVrr), DstReg).addReg(SrcReg, getKillRegState(KillSrc));
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return;
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}
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llvm_unreachable("Impossible reg-to-reg copy");
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}
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bool PTXInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DstReg, unsigned SrcReg,
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const TargetRegisterClass *DstRC,
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const TargetRegisterClass *SrcRC,
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DebugLoc DL) const {
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if (DstRC != SrcRC)
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return false;
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for (int i = 0, e = sizeof(map)/sizeof(map[0]); i != e; ++ i)
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if (DstRC == map[i].cls) {
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MachineInstr *MI = BuildMI(MBB, I, DL, get(map[i].opcode),
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DstReg).addReg(SrcReg);
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if (MI->findFirstPredOperandIdx() == -1) {
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MI->addOperand(MachineOperand::CreateReg(0, false));
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MI->addOperand(MachineOperand::CreateImm(/*IsInv=*/0));
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}
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return true;
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}
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return false;
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}
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bool PTXInstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
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switch (MI.getOpcode()) {
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default:
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return false;
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case PTX::MOVpp:
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case PTX::MOVrr:
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assert(MI.getNumOperands() >= 2 &&
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MI.getOperand(0).isReg() && MI.getOperand(1).isReg() &&
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"Invalid register-register move instruction");
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SrcSubIdx = DstSubIdx = 0; // No sub-registers
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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return true;
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}
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}
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