forked from OSchip/llvm-project
156 lines
6.8 KiB
YAML
156 lines
6.8 KiB
YAML
# RUN: llc -mtriple=armv8.1m.main -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
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# CHECK: entry:
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# CHECK: $lr = t2DLS
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# CHECK: for.body:
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# CHECK: $lr = t2LEUpdate renamable $lr
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--- |
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8.1m.main-unknown-unknown"
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; Function Attrs: norecurse nounwind
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define dso_local arm_aapcscc void @size_limit(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) local_unnamed_addr #0 {
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entry:
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%cmp8 = icmp eq i32 %N, 0
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br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader
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for.body.preheader: ; preds = %entry
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%scevgep = getelementptr i32, i32* %a, i32 -1
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%scevgep4 = getelementptr i32, i32* %c, i32 -1
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%scevgep8 = getelementptr i32, i32* %b, i32 -1
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call void @llvm.set.loop.iterations.i32(i32 %N)
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br label %for.body
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for.cond.cleanup: ; preds = %for.body, %entry
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ret void
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for.body: ; preds = %for.body, %for.body.preheader
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%lsr.iv9 = phi i32* [ %scevgep8, %for.body.preheader ], [ %scevgep10, %for.body ]
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%lsr.iv5 = phi i32* [ %scevgep4, %for.body.preheader ], [ %scevgep6, %for.body ]
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%lsr.iv1 = phi i32* [ %scevgep, %for.body.preheader ], [ %scevgep2, %for.body ]
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%0 = phi i32 [ %N, %for.body.preheader ], [ %3, %for.body ]
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%size = call i32 @llvm.arm.space(i32 4070, i32 undef)
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%scevgep11 = getelementptr i32, i32* %lsr.iv9, i32 1
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%1 = load i32, i32* %scevgep11, align 4, !tbaa !3
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%scevgep7 = getelementptr i32, i32* %lsr.iv5, i32 1
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%2 = load i32, i32* %scevgep7, align 4, !tbaa !3
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%mul = mul nsw i32 %2, %1
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%scevgep3 = getelementptr i32, i32* %lsr.iv1, i32 1
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store i32 %mul, i32* %scevgep3, align 4, !tbaa !3
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%scevgep2 = getelementptr i32, i32* %lsr.iv1, i32 1
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%scevgep6 = getelementptr i32, i32* %lsr.iv5, i32 1
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%scevgep10 = getelementptr i32, i32* %lsr.iv9, i32 1
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%3 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)
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%4 = icmp ne i32 %3, 0
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br i1 %4, label %for.body, label %for.cond.cleanup
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}
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; Function Attrs: nounwind
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declare i32 @llvm.arm.space(i32, i32) #1
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; Function Attrs: noduplicate nounwind
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declare void @llvm.set.loop.iterations.i32(i32) #2
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; Function Attrs: noduplicate nounwind
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #2
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; Function Attrs: nounwind
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declare void @llvm.stackprotector(i8*, i8**) #1
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attributes #0 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+ras,+soft-float,+strict-align,+thumb-mode,-crypto,-d32,-dotprod,-fp-armv8,-fp-armv8d16,-fp-armv8d16sp,-fp-armv8sp,-fp16,-fp16fml,-fp64,-fpregs,-fullfp16,-neon,-vfp2,-vfp2d16,-vfp2d16sp,-vfp2sp,-vfp3,-vfp3d16,-vfp3d16sp,-vfp3sp,-vfp4,-vfp4d16,-vfp4d16sp,-vfp4sp" "unsafe-fp-math"="false" "use-soft-float"="true" }
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attributes #1 = { nounwind }
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attributes #2 = { noduplicate nounwind }
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!llvm.module.flags = !{!0, !1}
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!llvm.ident = !{!2}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 1, !"min_enum_size", i32 4}
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!2 = !{!"clang version 9.0.0 (http://llvm.org/git/clang.git a9c7c0fc5d468f3d18a5c6beb697ab0d5be2ff4c) (http://llvm.org/git/llvm.git f34bff0c141a04a5182d57e2cfb1e4bc582c81b0)"}
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!3 = !{!4, !4, i64 0}
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!4 = !{!"int", !5, i64 0}
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!5 = !{!"omnipotent char", !6, i64 0}
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!6 = !{!"Simple C/C++ TBAA"}
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...
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---
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name: size_limit
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alignment: 1
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: false
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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- { reg: '$r3', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 8
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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successors: %bb.1(0x80000000)
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frame-setup tPUSH 14, $noreg, $r7, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 8
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r7, -8
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$r7 = frame-setup tMOVr $sp, 14, $noreg
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frame-setup CFI_INSTRUCTION def_cfa_register $r7
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tCMPi8 $r3, 0, 14, $noreg, implicit-def $cpsr
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t2IT 0, 8, implicit-def $itstate
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tPOP_RET 0, killed $cpsr, def $r7, def $pc, implicit killed $itstate
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renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg
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renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
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renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14, $noreg
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$lr = tMOVr $r3, 14, $noreg
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t2DoLoopStart killed $r3
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bb.1.for.body:
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successors: %bb.1(0x7c000000), %bb.2(0x04000000)
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dead renamable $r3 = SPACE 4070, undef renamable $r0
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renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep11, !tbaa !3)
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renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14, $noreg :: (load 4 from %ir.scevgep7, !tbaa !3)
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renamable $r3 = nsw t2MUL killed renamable $r3, killed renamable $r12, 14, $noreg
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early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep3, !tbaa !3)
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renamable $lr = t2LoopDec killed renamable $lr, 1
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t2LoopEnd renamable $lr, %bb.1
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tB %bb.2, 14, $noreg
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bb.2.for.cond.cleanup:
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tPOP_RET 14, $noreg, def $r7, def $pc
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...
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