forked from OSchip/llvm-project
190 lines
7.4 KiB
LLVM
190 lines
7.4 KiB
LLVM
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,LOOP %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,NOLOOP,GFX10 %s
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; Minimum offset
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; GCN-LABEL: {{^}}gws_barrier_offset0:
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; NOLOOP-DAG: s_load_dword [[BAR_NUM:s[0-9]+]]
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; NOLOOP-DAG: s_mov_b32 m0, -1{{$}}
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; NOLOOP: v_mov_b32_e32 v0, [[BAR_NUM]]
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; NOLOOP: ds_gws_barrier v0 offset:1 gds{{$}}
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; LOOP: [[LOOP:BB[0-9]+_[0-9]+]]:
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; LOOP-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 8, 1), 0
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; LOOP-NEXT: ds_gws_barrier v0 offset:1 gds
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; LOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; LOOP-NEXT: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_TRAPSTS, 8, 1)
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; LOOP-NEXT: s_cmp_lg_u32 [[GETREG]], 0
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; LOOP-NEXT: s_cbranch_scc1 [[LOOP]]
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define amdgpu_kernel void @gws_barrier_offset0(i32 %val) #0 {
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call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 0)
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ret void
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}
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; Maximum offset
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; GCN-LABEL: {{^}}gws_barrier_offset63:
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; NOLOOP-DAG: s_load_dword [[BAR_NUM:s[0-9]+]]
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; NOLOOP-DAG: s_mov_b32 m0, -1{{$}}
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; NOLOOP-DAG: v_mov_b32_e32 v0, [[BAR_NUM]]
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; NOLOOP: ds_gws_barrier v0 offset:64 gds{{$}}
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define amdgpu_kernel void @gws_barrier_offset63(i32 %val) #0 {
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call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 63)
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ret void
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}
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; FIXME: Should be able to shift directly into m0
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; GCN-LABEL: {{^}}gws_barrier_sgpr_offset:
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; NOLOOP-DAG: s_load_dwordx2 s{{\[}}[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]{{\]}}
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; NOLOOP-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16
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; NOLOOP-DAG: s_mov_b32 m0, [[SHL]]{{$}}
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; NOLOOP-DAG: v_mov_b32_e32 v0, s[[BAR_NUM]]
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; NOLOOP: ds_gws_barrier v0 gds{{$}}
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define amdgpu_kernel void @gws_barrier_sgpr_offset(i32 %val, i32 %offset) #0 {
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call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 %offset)
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ret void
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}
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; Variable offset in SGPR with constant add
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; GCN-LABEL: {{^}}gws_barrier_sgpr_offset_add1:
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; NOLOOP-DAG: s_load_dwordx2 s{{\[}}[[BAR_NUM:[0-9]+]]:[[OFFSET:[0-9]+]]{{\]}}
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; NOLOOP-DAG: s_lshl_b32 [[SHL:s[0-9]+]], s[[OFFSET]], 16
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; NOLOOP-DAG: s_mov_b32 m0, [[SHL]]{{$}}
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; NOLOOP-DAG: v_mov_b32_e32 v0, s[[BAR_NUM]]
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; NOLOOP: ds_gws_barrier v0 offset:1 gds{{$}}
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define amdgpu_kernel void @gws_barrier_sgpr_offset_add1(i32 %val, i32 %offset.base) #0 {
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%offset = add i32 %offset.base, 1
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call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 %offset)
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ret void
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}
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; GCN-LABEL: {{^}}gws_barrier_vgpr_offset:
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; NOLOOP-DAG: s_load_dword [[BAR_NUM:s[0-9]+]]
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; NOLOOP-DAG: v_readfirstlane_b32 [[READLANE:s[0-9]+]], v0
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; NOLOOP-DAG: s_lshl_b32 [[SHL:s[0-9]+]], [[READLANE]], 16
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; NOLOOP-DAG: s_mov_b32 m0, [[SHL]]{{$}}
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; NOLOOP-DAG: v_mov_b32_e32 v0, [[BAR_NUM]]
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; NOLOOP: ds_gws_barrier v0 gds{{$}}
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define amdgpu_kernel void @gws_barrier_vgpr_offset(i32 %val) #0 {
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%vgpr.offset = call i32 @llvm.amdgcn.workitem.id.x()
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call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 %vgpr.offset)
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ret void
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}
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; Variable offset in VGPR with constant add
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; GCN-LABEL: {{^}}gws_barrier_vgpr_offset_add:
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; NOLOOP-DAG: s_load_dword [[BAR_NUM:s[0-9]+]]
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; NOLOOP-DAG: v_readfirstlane_b32 [[READLANE:s[0-9]+]], v0
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; NOLOOP-DAG: s_lshl_b32 [[SHL:s[0-9]+]], [[READLANE]], 16
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; NOLOOP-DAG: s_mov_b32 m0, [[SHL]]{{$}}
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; NOLOOP-DAG: v_mov_b32_e32 v0, [[BAR_NUM]]
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; NOLOOP: ds_gws_barrier v0 offset:3 gds{{$}}
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define amdgpu_kernel void @gws_barrier_vgpr_offset_add(i32 %val) #0 {
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%vgpr.offset.base = call i32 @llvm.amdgcn.workitem.id.x()
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%vgpr.offset = add i32 %vgpr.offset.base, 3
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call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 %vgpr.offset)
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ret void
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}
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@lds = internal unnamed_addr addrspace(3) global i32 undef
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; Check if m0 initialization is shared
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; GCN-LABEL: {{^}}gws_barrier_save_m0_barrier_constant_offset:
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; NOLOOP: s_mov_b32 m0, -1
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; NOLOOP-NOT: s_mov_b32 m0
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define amdgpu_kernel void @gws_barrier_save_m0_barrier_constant_offset(i32 %val) #0 {
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store i32 1, i32 addrspace(3)* @lds
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call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 10)
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store i32 2, i32 addrspace(3)* @lds
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ret void
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}
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; Make sure this increments lgkmcnt
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; GCN-LABEL: {{^}}gws_barrier_lgkmcnt:
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; NOLOOP: ds_gws_barrier v0 offset:1 gds{{$}}
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; NOLOOP-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)
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; NOLOOP-NEXT: s_setpc_b64
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define void @gws_barrier_lgkmcnt(i32 %val) {
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call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 0)
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ret void
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}
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; Does not imply memory fence on its own
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; GCN-LABEL: {{^}}gws_barrier_wait_before:
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; NOLOOP: s_waitcnt
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; NOLOOP-NOT: s_waitcnt{{$}}
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define amdgpu_kernel void @gws_barrier_wait_before(i32 %val, i32 addrspace(1)* %ptr) #0 {
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store i32 0, i32 addrspace(1)* %ptr
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call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 7)
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ret void
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}
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; GCN-LABEL: {{^}}gws_barrier_wait_after:
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; NOLOOP: ds_gws_barrier v0 offset:8 gds
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; NOLOOP-NEXT: s_waitcnt expcnt(0){{$}}
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; NOLOOP-NEXT: load_dword
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define amdgpu_kernel void @gws_barrier_wait_after(i32 %val, i32 addrspace(1)* %ptr) #0 {
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call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 7)
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%load = load volatile i32, i32 addrspace(1)* %ptr
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ret void
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}
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; Does not imply memory fence on its own
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; GCN-LABEL: {{^}}gws_barrier_fence_before:
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; NOLOOP: store_dword
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; NOLOOP: s_waitcnt vmcnt(0) lgkmcnt(0)
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; NOLOOP: ds_gws_barrier v0 offset:8 gds
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define amdgpu_kernel void @gws_barrier_fence_before(i32 %val, i32 addrspace(1)* %ptr) #0 {
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store i32 0, i32 addrspace(1)* %ptr
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fence release
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call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 7)
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ret void
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}
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; GCN-LABEL: {{^}}gws_barrier_fence_after:
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; NOLOOP: ds_gws_barrier v0 offset:8 gds
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; NOLOOP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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; NOLOOP-NEXT: load_dword
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define amdgpu_kernel void @gws_barrier_fence_after(i32 %val, i32 addrspace(1)* %ptr) #0 {
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call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 7)
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fence release
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%load = load volatile i32, i32 addrspace(1)* %ptr
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ret void
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}
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; FIXME: Should a wait be inserted here, or is an explicit fence needed?
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; GCN-LABEL: {{^}}gws_init_barrier:
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; NOLOOP: s_mov_b32 m0, -1
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; NOLOOP: ds_gws_init v0 offset:8 gds
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; NOLOOP-NEXT: ds_gws_barrier v0 offset:8 gds
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define amdgpu_kernel void @gws_init_barrier(i32 %val) #0 {
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call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 7)
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call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 7)
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ret void
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}
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; FIXME: Why vmcnt, not expcnt?
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; GCN-LABEL: {{^}}gws_init_fence_barrier:
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; NOLOOP: s_mov_b32 m0, -1
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; NOLOOP: ds_gws_init v0 offset:8 gds
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; NOLOOP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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; NOLOOP-NEXT: ds_gws_barrier v0 offset:8 gds
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define amdgpu_kernel void @gws_init_fence_barrier(i32 %val) #0 {
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call void @llvm.amdgcn.ds.gws.init(i32 %val, i32 7)
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fence release
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call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 7)
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ret void
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}
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declare void @llvm.amdgcn.ds.gws.barrier(i32, i32) #1
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declare void @llvm.amdgcn.ds.gws.init(i32, i32) #2
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declare i32 @llvm.amdgcn.workitem.id.x() #3
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attributes #0 = { nounwind }
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attributes #1 = { convergent inaccessiblememonly nounwind }
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attributes #2 = { convergent inaccessiblememonly nounwind writeonly }
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attributes #3 = { nounwind readnone speculatable }
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