forked from OSchip/llvm-project
160 lines
6.1 KiB
YAML
160 lines
6.1 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN,SI,SICI,SIVI
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# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN,CI,SICI
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN,VI,SIVI
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# REQUIRES: global-isel
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--- |
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define amdgpu_kernel void @smrd_imm(i32 addrspace(4)* %const0) { ret void }
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...
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---
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name: smrd_imm
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legalized: true
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regBankSelected: true
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# GCN: body:
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# GCN: [[PTR:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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# Immediate offset:
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# SICI: S_LOAD_DWORD_IMM [[PTR]], 1, 0, 0
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# VI: S_LOAD_DWORD_IMM [[PTR]], 4, 0, 0
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# Max immediate offset for SI
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# SICI: S_LOAD_DWORD_IMM [[PTR]], 255, 0, 0
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# VI: S_LOAD_DWORD_IMM [[PTR]], 1020, 0, 0
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# Immediate overflow for SI
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# SI: [[K1024:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1024
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# SI: S_LOAD_DWORD_SGPR [[PTR]], [[K1024]], 0
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# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 256, 0
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# VI: S_LOAD_DWORD_IMM [[PTR]], 1024, 0
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# Max immediate offset for VI
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# SI: [[K1048572:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1048572
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# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 262143
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# VI: S_LOAD_DWORD_IMM [[PTR]], 1048572
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#
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# Immediate overflow for VI
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# SIVI: [[K1048576:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1048576
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# SIVI: S_LOAD_DWORD_SGPR [[PTR]], [[K1048576]], 0
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# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 262144, 0
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# Max immediate for CI
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# SIVI: [[K_LO:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4294967292
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# SIVI: [[K_HI:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 3
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# SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1
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# SIVI-DAG: [[K_SUB0:%[0-9]+]]:sgpr_32 = COPY [[K]].sub0
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# SIVI-DAG: [[PTR_LO:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub0
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# SIVI: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
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# SIVI-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1
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# SIVI-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1
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# SIVI: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
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# SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1
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# SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0, 0
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# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 4294967295, 0, 0
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# Immediate overflow for CI
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# GCN: [[K_LO:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0
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# GCN: [[K_HI:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4
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# GCN: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1
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# GCN-DAG: [[K_SUB0:%[0-9]+]]:sgpr_32 = COPY [[K]].sub0
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# GCN-DAG: [[PTR_LO:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub0
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# GCN: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
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# GCN-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1
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# GCN-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1
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# GCN: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
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# GCN: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1
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# GCN: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0, 0
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# Max 32-bit byte offset
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# SIVI: [[K4294967292:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4294967292
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# SIVI: S_LOAD_DWORD_SGPR [[PTR]], [[K4294967292]], 0
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# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 1073741823, 0
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# Overflow 32-bit byte offset
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# SIVI: [[K_LO:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0
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# SIVI: [[K_HI:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1
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# SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1
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# SIVI-DAG: [[K_SUB0:%[0-9]+]]:sgpr_32 = COPY [[K]].sub0
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# SIVI-DAG: [[PTR_LO:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub0
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# SIVI: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
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# SIVI-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1
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# SIVI-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1
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# SIVI: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
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# SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1
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# SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0, 0
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# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 1073741824, 0, 0
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# Pointer loads
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# GCN: [[AS0:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0
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# GCN: $sgpr0_sgpr1 = COPY [[AS0]]
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# GCN: [[AS1:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0
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# GCN: $sgpr0_sgpr1 = COPY [[AS1]]
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# GCN: [[AS4:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0
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# GCN: $sgpr0_sgpr1 = COPY [[AS4]]
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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%0:sgpr(p4) = COPY $sgpr0_sgpr1
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%1:sgpr(s64) = G_CONSTANT i64 4
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%2:sgpr(p4) = G_GEP %0, %1
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%3:sgpr(s32) = G_LOAD %2 :: (load 4 from %ir.const0, addrspace 4)
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$sgpr0 = COPY %3
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%4:sgpr(s64) = G_CONSTANT i64 1020
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%5:sgpr(p4) = G_GEP %0, %4
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%6:sgpr(s32) = G_LOAD %5 :: (load 4 from %ir.const0, addrspace 4)
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$sgpr0 = COPY %6
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%7:sgpr(s64) = G_CONSTANT i64 1024
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%8:sgpr(p4) = G_GEP %0, %7
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%9:sgpr(s32) = G_LOAD %8 :: (load 4 from %ir.const0, addrspace 4)
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$sgpr0 = COPY %9
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%10:sgpr(s64) = G_CONSTANT i64 1048572
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%11:sgpr(p4) = G_GEP %0, %10
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%12:sgpr(s32) = G_LOAD %11 :: (load 4 from %ir.const0, addrspace 4)
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$sgpr0 = COPY %12
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%13:sgpr(s64) = G_CONSTANT i64 1048576
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%14:sgpr(p4) = G_GEP %0, %13
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%15:sgpr(s32) = G_LOAD %14 :: (load 4 from %ir.const0, addrspace 4)
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$sgpr0 = COPY %15
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%16:sgpr(s64) = G_CONSTANT i64 17179869180
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%17:sgpr(p4) = G_GEP %0, %16
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%18:sgpr(s32) = G_LOAD %17 :: (load 4 from %ir.const0, addrspace 4)
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$sgpr0 = COPY %18
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%19:sgpr(s64) = G_CONSTANT i64 17179869184
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%20:sgpr(p4) = G_GEP %0, %19
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%21:sgpr(s32) = G_LOAD %20 :: (load 4 from %ir.const0, addrspace 4)
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$sgpr0 = COPY %21
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%22:sgpr(s64) = G_CONSTANT i64 4294967292
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%23:sgpr(p4) = G_GEP %0, %22
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%24:sgpr(s32) = G_LOAD %23 :: (load 4 from %ir.const0, addrspace 4)
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$sgpr0 = COPY %24
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%25:sgpr(s64) = G_CONSTANT i64 4294967296
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%26:sgpr(p4) = G_GEP %0, %25
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%27:sgpr(s32) = G_LOAD %26 :: (load 4 from %ir.const0, addrspace 4)
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$sgpr0 = COPY %27
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%28:sgpr(p0) = G_LOAD %0 :: (load 8 from %ir.const0, addrspace 4)
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$sgpr0_sgpr1 = COPY %28
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%29:sgpr(p1) = G_LOAD %0 :: (load 8 from %ir.const0, addrspace 4)
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$sgpr0_sgpr1 = COPY %29
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%30:sgpr(p4) = G_LOAD %0 :: (load 8 from %ir.const0, addrspace 4)
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$sgpr0_sgpr1 = COPY %30
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...
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---
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