Matt Arsenault fae05692a3 CodeGen: Print/parse LLTs in MachineMemOperands ... This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.		2021-06-30 16:54:13 -04:00
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generic-vreg-undef-use.mir	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
live-ins-01.mir	…
live-ins-02.mir	…
live-ins-03.mir	…
test_copy.mir	…
test_copy_mismatch_types.mir	…
test_copy_physregs_x86.mir	GlobalISel: Relax verification of physical register copy types	2021-04-28 08:45:41 -04:00
test_g_add.mir	…
test_g_addrspacecast.mir	…
test_g_assert_sext.mir	[GlobalISel] Add G_ASSERT_SEXT	2021-02-17 13:10:34 -08:00
test_g_assert_sext_register_bank_class.mir	[GlobalISel] Add G_ASSERT_SEXT	2021-02-17 13:10:34 -08:00
test_g_assert_zext.mir	[GlobalISel] Simpler verification of G_SEXT_INREG and G_ASSERT_ZEXT	2021-02-12 21:33:27 +00:00
test_g_assert_zext_register_bank_class.mir	…
test_g_bitcast.mir	…
test_g_brindirect_is_indirect_branch.mir	…
test_g_brjt.mir	…
test_g_brjt_is_indirect_branch.mir	…
test_g_build_vector.mir	…
test_g_build_vector_trunc.mir	…
test_g_bzero.mir	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
test_g_concat_vectors.mir	GlobalISel: Verify G_CONCAT_VECTORS has at least 2 sources	2021-03-01 09:10:36 -05:00
test_g_constant.mir	…
test_g_dyn_stackalloc.mir	…
test_g_extract.mir	…
test_g_fcmp.mir	…
test_g_fconstant.mir	…
test_g_icmp.mir	…
test_g_insert.mir	…
test_g_intrinsic.mir	…
test_g_intrinsic_w_side_effects.mir	…
test_g_inttoptr.mir	…
test_g_jump_table.mir	…
test_g_load.mir	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
test_g_memcpy.mir	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
test_g_memcpy_inline.mir	[GISel] Support llvm.memcpy.inline	2021-06-30 12:39:05 -07:00
test_g_memmove.mir	[GISel] Support llvm.memcpy.inline	2021-06-30 12:39:05 -07:00
test_g_memset.mir	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
test_g_merge_values.mir	…
test_g_phi.mir	…
test_g_ptr_add.mir	…
test_g_ptrmask.mir	…
test_g_ptrtoint.mir	…
test_g_rotr_rotl.mir	[GlobalISel] Add G_ROTR and G_ROTL opcodes for rotates.	2021-03-25 17:23:30 -07:00
test_g_select.mir	…
test_g_sext_inreg.mir	[GlobalISel] Simpler verification of G_SEXT_INREG and G_ASSERT_ZEXT	2021-02-12 21:33:27 +00:00
test_g_sextload.mir	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
test_g_shuffle_vector.mir	…
test_g_store.mir	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
test_g_trunc.mir	…
test_g_ubfx_sbfx.mir	Add missing -march to runline in llvm/test/MachineVerifier/test_g_ubfx_sbfx.mir	2021-03-24 11:23:08 -07:00
test_g_zextload.mir	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
test_phis_precede_nonphis.mir	…
test_vector_reductions.mir	…
verifier-generic-extend-truncate.mir	…
verifier-generic-types-1.mir	…
verifier-generic-types-2.mir	…
verifier-implicit-virtreg-invalid-physreg-liveness.mir	…
verifier-phi-fail0.mir	…
verifier-phi.mir	…
verifier-pseudo-terminators.mir	…
verifier-statepoint.mir	…
verify-regbankselected.mir	…
verify-regops.mir	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
verify-selected.mir	…