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llvm-project/llvm/test/CodeGen
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Simon Pilgrim 0aece73aba [DAG] Fold select(cond,binop(x,y),binop(x,z)) -> binop(x,select(cond,y,z)) 
Similar to the folds performed in InstCombinerImpl::foldSelectOpOp, this attempts to push a select further up to help merge a pair of binops.

I'm primarily interested in select(cond,add(x,y),add(x,z)) folds to help expose pointer math (see https://bugs.llvm.org/show_bug.cgi?id=51069 etc.) but I've tried to use the more generic isBinOp().

Differential Revision: https://reviews.llvm.org/D106058
 		2021-07-15 16:08:30 +01:00
..
AArch64 [AArch64][GlobalISel] Optimise lowering for some vector types for min/max 2021-07-15 11:34:32 +01:00
AMDGPU [AMDGPU] Use update_test_checks.py script for annotate kernel features tests. 2021-07-15 03:13:37 +03:00
ARC
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ARM ARM: reuse existing libcall global variable if possible. 2021-07-14 14:14:47 +01:00
AVR Place the BlockAddress type in the address space of the containing function 2021-07-02 12:17:55 +01:00
BPF [InstCombine] Fold (select C, (gep Ptr, Idx), Ptr) -> (gep Ptr, (select C, Idx, 0)) (PR50183) (REAPPLIED) 2021-07-14 12:21:01 +01:00
Generic [llc] Default MCUseDwarfDirectory to true 2021-07-12 17:44:02 -07:00
Hexagon [DAG] Reassociate Add with Or 2021-07-07 10:21:07 +01:00
Inputs
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Lanai CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
M68k [M68k][GloballSel] Lower outgoing return values in IRTranslator 2021-07-05 11:39:09 -07:00
MIR CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
MSP430 Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
Mips [MIPS] Refresh ashr test checks. NFCI. 2021-07-15 12:12:19 +01:00
NVPTX [NVPTX] Tweak fast-math tests to avoid select(binop(x,y),binop(x,z)) fold 2021-07-15 15:42:25 +01:00
PowerPC [2/2][RemoveRedundantDebugValues] Add a Pass that removes redundant DBG_VALUEs 2021-07-15 00:08:31 -07:00
RISCV [RISCV] Fix the neutral element in vector 'fadd' reductions 2021-07-14 10:18:38 +01:00
SPARC CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
SystemZ [SystemZ] Bugfix for the 'N' code for inline asm operand. 2021-07-12 15:04:08 +02:00
Thumb CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
Thumb2 [ARM] Expand types handled in VQDMULH recognition 2021-07-15 14:47:53 +01:00
VE [LegalizeTypes][VE] Don't Expand BITREVERSE/BSWAP during type legalization promotion if they will be promoted for NVT in op legalization. 2021-06-29 11:00:11 -07:00
WebAssembly [WebAssembly] Codegen for v128.storeX_lane instructions 2021-07-14 16:15:25 -07:00
WinCFGuard Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
WinEH Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
X86 [DAG] Fold select(cond,binop(x,y),binop(x,z)) -> binop(x,select(cond,y,z)) 2021-07-15 16:08:30 +01:00
XCore Update @llvm.powi to handle different int sizes for the exponent 2021-06-17 09:38:28 +02:00