forked from OSchip/llvm-project
104 lines
2.8 KiB
LLVM
104 lines
2.8 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,SIVI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GFX89,SIVI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX89 %s
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; GCN-LABEL: {{^}}v_mul_i16:
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; SI: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}}
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; SI: v_and_b32_e32 v{{[0-9]+}}, [[K]]
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; SI: v_and_b32_e32 v{{[0-9]+}}, [[K]]
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; SI: v_mul_u32_u24
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; GFX89: v_mul_lo_u16_e32 v0, v0, v1
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define i16 @v_mul_i16(i16 %a, i16 %b) {
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%r.val = mul i16 %a, %b
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ret i16 %r.val
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}
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; FIXME: Should emit scalar mul or maybe i16 v_mul here
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; GCN-LABEL: {{^}}s_mul_i16:
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; GCN: v_mul_u32_u24
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define amdgpu_kernel void @s_mul_i16(i16 %a, i16 %b) {
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%r.val = mul i16 %a, %b
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store volatile i16 %r.val, i16 addrspace(1)* null
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ret void
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}
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; FIXME: Should emit u16 mul here. Instead it's worse than SI
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; GCN-LABEL: {{^}}v_mul_i16_uniform_load:
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; SI: v_mul_u32_u24
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; GFX89: v_mul_lo_i32
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define amdgpu_kernel void @v_mul_i16_uniform_load(
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i16 addrspace(1)* %r,
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i16 addrspace(1)* %a,
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i16 addrspace(1)* %b) {
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entry:
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%a.val = load i16, i16 addrspace(1)* %a
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%b.val = load i16, i16 addrspace(1)* %b
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%r.val = mul i16 %a.val, %b.val
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store i16 %r.val, i16 addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}v_mul_v2i16:
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; SI: v_mul_lo_i32
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; SI: v_mul_lo_i32
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; VI: v_mul_lo_u16_sdwa
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; VI: v_mul_lo_u16_e32
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; VI: v_or_b32_e32
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; GFX9: s_waitcnt
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; GFX9-NEXT: v_pk_mul_lo_u16 v0, v0, v1
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; GFX9-NEXT: s_setpc_b64
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define <2 x i16> @v_mul_v2i16(<2 x i16> %a, <2 x i16> %b) {
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%r.val = mul <2 x i16> %a, %b
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ret <2 x i16> %r.val
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}
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; FIXME: Unpack garbage on gfx9
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; GCN-LABEL: {{^}}v_mul_v3i16:
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; SI: v_mul_lo_i32
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; SI: v_mul_lo_i32
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; SI: v_mul_lo_i32
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; VI: v_mul_lo_u16
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; VI: v_mul_lo_u16
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; VI: v_mul_lo_u16
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; GFX9: v_and_b32
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; GFX9: v_and_b32
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; GFX9: v_lshl_or_b32
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; GFX9: v_lshl_or_b32
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; GFX9: v_lshl_or_b32
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; GFX9: v_pk_mul_lo_u16
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; GFX9: v_pk_mul_lo_u16
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; GFX9: s_setpc_b64
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define <3 x i16> @v_mul_v3i16(<3 x i16> %a, <3 x i16> %b) {
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%r.val = mul <3 x i16> %a, %b
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ret <3 x i16> %r.val
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}
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; GCN-LABEL: {{^}}v_mul_v4i16:
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; SI: v_mul_lo_i32
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; SI: v_mul_lo_i32
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; SI: v_mul_lo_i32
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; SI: v_mul_lo_i32
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; VI: v_mul_lo_u16_sdwa
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; VI: v_mul_lo_u16_e32
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; VI: v_mul_lo_u16_sdwa
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; VI: v_mul_lo_u16_e32
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; VI: v_or_b32_e32
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; VI: v_or_b32_e32
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; GFX9: s_waitcnt
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; GFX9-NEXT: v_pk_mul_lo_u16 v0, v0, v2
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; GFX9-NEXT: v_pk_mul_lo_u16 v1, v1, v3
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; GFX9-NEXT: s_setpc_b64
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define <4 x i16> @v_mul_v4i16(<4 x i16> %a, <4 x i16> %b) {
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%r.val = mul <4 x i16> %a, %b
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ret <4 x i16> %r.val
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}
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