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Craig Topper e2cd92cb9b [RISCV] Match splatted load to scalar load + splat. Form strided load during isel. 
This modifies my previous patch to push the strided load formation
to isel. This gives us opportunity to fold the splat into a .vx
operation first. Using a scalar register and a .vx operation reduces
vector register pressure which can be important for larger LMULs.

If we can't fold the splat into a .vx operation, then it can make
sense to use a strided load to free up the vector arithmetic
ALU to do actual arithmetic rather than tying it up with vmv.v.x.

Reviewed By: khchen

Differential Revision: https://reviews.llvm.org/D101138
 		2021-04-26 13:32:03 -07:00
..
Analysis [AArch64] Add AArch64TTIImpl::getMaskedMemoryOpCost function 2021-04-26 11:00:03 +01:00
Assembler [LLParser] Print mismatched types in error message 2021-04-21 13:10:37 -07:00
Bindings [OCaml][Test] Fix and enable debuginfo.ml test 2021-03-28 06:25:39 +05:30
Bitcode [clang][AArch64] Correctly align HFA arguments when passed on the stack 2021-04-15 22:58:14 +01:00
BugPoint
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CodeGen [RISCV] Match splatted load to scalar load + splat. Form strided load during isel. 2021-04-26 13:32:03 -07:00
DebugInfo [DebugInfo][AIX] Set target debugger-tune default to dbx 2021-04-26 01:38:44 +00:00
Demangle
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Examples [Orc][examples] Add missing FileCheck for lit test and polish output 2021-04-07 11:12:20 +02:00
ExecutionEngine [JITLink] Add testcase that was accidentally left out of 19e402d2b3. 2021-04-17 11:55:55 -07:00
Feature [FunctionAttrs] Force old pm in test so it doens't behave differently depending on the configuration setting for this flag 2021-04-09 11:46:19 +02:00
FileCheck Fix PR46880: Fail CHECK-NOT with undefined variable 2021-04-20 14:42:46 +01:00
Instrumentation [IR][sanitizer] Add module flag "frame-pointer" and set it for cc1 -mframe-pointer={non-leaf,all} 2021-04-22 18:07:30 -07:00
Integer Re-apply "[lli] Make -jit-kind=orc the default JIT engine" 2021-03-30 12:08:26 +02:00
JitListener
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LTO Remove dead CHECK-ERR line. 2021-03-30 09:31:00 -07:00
Linker Preserve the lexical order for global variables during llvm-link merge 2021-04-26 10:11:34 -07:00
MC [ARM][disassembler] Fix incorrect number of MCOperands generated by the disassembler 2021-04-25 11:55:10 -07:00
MachineVerifier [GlobalISel] Add G_ROTR and G_ROTL opcodes for rotates. 2021-03-25 17:23:30 -07:00
Object [yaml2obj/obj2yaml/llvm-readobj] Support printing and parsing AVR-specific e_flags 2021-04-15 15:54:28 +02:00
ObjectYAML [lld] Fixed CodeView GuidAdapter::format to handle GUID bytes in the right order. 2021-04-09 05:29:14 +04:00
Other [OpenMP] Add OpenMPOpt as a Module pass 2021-04-20 12:28:58 -04:00
SafepointIRVerifier
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Support [llvm-objdump] Switch command-line parsing from llvm::cl to OptTable 2021-04-14 20:12:24 -04:00
SymbolRewriter
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TableGen [TableGen] Add support for the 'assert' statement in multiclasses 2021-04-19 09:01:42 -04:00
ThinLTO/X86 Preserve the lexical order for global variables during llvm-link merge 2021-04-26 10:11:34 -07:00
Transforms [gcov] Set nounwind and respect module flags metadata "frame-pointer" & "uwtable" for synthesized functions 2021-04-26 13:30:21 -07:00
Unit
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Verifier [X86][AMX] Verify illegal types or instructions for x86_amx. 2021-04-20 16:14:22 +08:00
YAMLParser
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tools Support DW_FORM_strx* in llvm-dwp. 2021-04-26 12:32:45 -07:00
.clang-format
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CMakeLists.txt [llvm-rc] Add a GNU windres-like frontend to llvm-rc 2021-04-26 22:04:29 +03:00
TestRunner.sh
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lit.cfg.py [llvm-rc] Add a GNU windres-like frontend to llvm-rc 2021-04-26 22:04:29 +03:00
lit.site.cfg.py.in
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