llvm-project/llvm/lib/CodeGen
Fangrui Song c5d38924dc [XRay] xray_fn_idx: set SHF_WRITE to avoid text relocations
In a future change we should properly fix xray_fn_idx to use PC-relative
addresses as well, but for now let's keep absolute addresses until sled
addresses are all fixed.
2020-04-21 12:02:29 -07:00
..
AsmPrinter [XRay] xray_fn_idx: set SHF_WRITE to avoid text relocations 2020-04-21 12:02:29 -07:00
GlobalISel [GlobalISel] Introduce InlineAsmLowering class 2020-04-20 15:10:18 +02:00
MIRParser [cmake] LLVMMIRParser - add include/llvm/CodeGen/LLVMMIRParser header path 2020-04-18 12:31:41 +01:00
SelectionDAG [CodeGen] Support freeze expand for ppc_fp128 2020-04-20 07:27:41 +00:00
AggressiveAntiDepBreaker.cpp [AntidepBreaker] Move AntiDepBreaker to include folder. 2020-04-14 11:40:57 -07:00
AggressiveAntiDepBreaker.h [AntidepBreaker] Move AntiDepBreaker to include folder. 2020-04-14 11:40:57 -07:00
AllocationOrder.cpp
AllocationOrder.h
Analysis.cpp [CallSite removal][CodeGen] Replace ImmutableCallSite with CallBase in isInTailCallPosition. 2020-04-13 23:04:57 -07:00
AtomicExpandPass.cpp [NFC] Modernize misc. uses of Align/MaybeAlign APIs. 2020-04-06 17:53:04 -07:00
BBSectionsPrepare.cpp Extend BasicBlock sections to allow specifying clusters of basic blocks in the same section. 2020-04-13 12:19:59 -07:00
BasicTargetTransformInfo.cpp
BranchFolding.cpp BranchFolding.h - cleanup includes and forward declarations. NFC. 2020-04-20 15:59:39 +01:00
BranchFolding.h BranchFolding.h - cleanup includes and forward declarations. NFC. 2020-04-20 15:59:39 +01:00
BranchRelaxation.cpp [BranchRelaxation] Simplify offset computation and fix a bug in adjustBlockOffsets() 2020-01-19 16:02:16 -08:00
BreakFalseDeps.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
BuiltinGCs.cpp
CFGuardLongjmp.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
CFIInstrInserter.cpp Revert "Generate Callee Saved Register (CSR) related cfi directives like .cfi_restore." 2020-03-19 22:45:27 -07:00
CMakeLists.txt Split LiveRangeCalc in LiveRangeCalc/LiveIntervalCalc. NFC 2020-04-10 11:26:21 -07:00
CalcSpillWeights.cpp Fix possible assertion when using PBQP with debug info 2020-03-18 15:29:42 +03:00
CallingConvLower.cpp CodeGen: Use Register more in CallLowering 2020-04-08 12:10:58 -04:00
CodeGen.cpp Re-land [Codegen/Statepoint] Allow usage of registers for non gc deopt values. 2020-04-10 10:13:39 +07:00
CodeGenPrepare.cpp [Local] Update getOrEnforceKnownAlignment/getKnownAlignment to use Align/MaybeAlign. 2020-04-20 21:31:44 -07:00
CommandFlags.cpp CodeGen: Add -denormal-fp-math-f32 flag 2020-03-27 14:00:39 -07:00
CriticalAntiDepBreaker.cpp [AntidepBreaker] Move AntiDepBreaker to include folder. 2020-04-14 11:40:57 -07:00
CriticalAntiDepBreaker.h [AntidepBreaker] Move AntiDepBreaker to include folder. 2020-04-14 11:40:57 -07:00
DFAPacketizer.cpp [DFAPacketizer] Allow up to 64 functional units 2019-11-05 15:41:42 +00:00
DeadMachineInstructionElim.cpp [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. 2020-01-14 19:26:15 -05:00
DetectDeadLanes.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
DwarfEHPrepare.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
EarlyIfConversion.cpp [AArch64] Don't generate gpr CSEL instructions in early-ifcvt if regclasses aren't compatible. 2020-01-21 16:51:31 -08:00
EdgeBundles.cpp CodeGen/EdgeBundles - move Twine.h include down into EdgeBundles.cpp. NFC. 2020-04-11 12:21:04 +01:00
ExecutionDomainFix.cpp Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each 2019-10-19 01:31:09 +00:00
ExpandMemCmp.cpp [CallSite removal][TargetLibraryInfo] Replace ImmutableCallSite with CallBase in one of the getLibFunc signatures. NFC 2020-04-15 22:43:41 -07:00
ExpandPostRAPseudos.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
ExpandReductions.cpp Clean up usages of asserting vector getters in Type 2020-04-10 14:53:43 -07:00
FEntryInserter.cpp Make llvm::StringRef to std::string conversions explicit. 2020-01-28 23:25:25 +01:00
FaultMaps.cpp [MC] Add MCStreamer::emitInt{8,16,32,64} 2020-02-29 09:40:21 -08:00
FinalizeISel.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
FixupStatepointCallerSaved.cpp [Statepoint] Add getters to StatepointOpers. 2020-04-15 14:31:42 +03:00
FuncletLayout.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
GCMetadata.cpp Make llvm::StringRef to std::string conversions explicit. 2020-01-28 23:25:25 +01:00
GCMetadataPrinter.cpp
GCRootLowering.cpp CodeGen: Use Register in TargetFrameLowering 2020-04-07 17:07:44 -04:00
GCStrategy.cpp
GlobalMerge.cpp Make llvm::StringRef to std::string conversions explicit. 2020-01-28 23:25:25 +01:00
HardwareLoops.cpp Revert "[SCEV] Move ScalarEvolutionExpander.cpp to Transforms/Utils (NFC)." 2020-01-04 18:44:38 +00:00
IfConversion.cpp BranchFolding.h - cleanup includes and forward declarations. NFC. 2020-04-20 15:59:39 +01:00
ImplicitNullChecks.cpp Add OffsetIsScalable to getMemOperandWithOffset 2020-02-18 15:53:29 +00:00
IndirectBrExpandPass.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
InlineSpiller.cpp [InlineSpiller] simplify insertReload() NFC 2020-04-21 08:31:20 -07:00
InterferenceCache.cpp
InterferenceCache.h
InterleavedAccessPass.cpp Clean up usages of asserting vector getters in Type 2020-04-10 14:53:43 -07:00
InterleavedLoadCombinePass.cpp Upgrade calls to CreateShuffleVector to use the preferred form of passing an array of ints 2020-04-15 12:51:38 +02:00
IntrinsicLowering.cpp [CallSite removal][CodeGen] Use CallBase instead of ImmutableCallSite in IntrinsicLowering. NFC 2020-04-13 00:19:27 -07:00
LLVMBuild.txt
LLVMTargetMachine.cpp [MC] Default MCContext::UseNamesOnTempLabels to false and only set it to true for MCAsmStreamer 2020-02-25 18:23:10 -08:00
LatencyPriorityQueue.cpp
LazyMachineBlockFrequencyInfo.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
LexicalScopes.cpp [DebugInfo] Re-implement LexicalScopes dominance method, add unit tests 2020-02-28 11:41:28 +00:00
LiveDebugValues.cpp [LiveDebugValues] Terminate open ranges on DBG_VALUE $noreg 2020-04-16 10:26:47 +01:00
LiveDebugVariables.cpp [NFC] Fix performance issue in LiveDebugVariables 2020-04-02 09:39:33 +01:00
LiveDebugVariables.h
LiveInterval.cpp [LiveInterval] Allow updating subranges with slightly out-dated IR 2019-11-13 11:17:56 -08:00
LiveIntervalCalc.cpp Split LiveRangeCalc in LiveRangeCalc/LiveIntervalCalc. NFC 2020-04-10 11:26:21 -07:00
LiveIntervalUnion.cpp
LiveIntervals.cpp [LiveIntervals] Replace handleMoveIntoBundle 2020-04-16 19:58:19 +09:00
LivePhysRegs.cpp [ARM][LowOverheadLoops] Update liveness info 2020-01-16 15:44:25 +00:00
LiveRangeCalc.cpp Split LiveRangeCalc in LiveRangeCalc/LiveIntervalCalc. NFC 2020-04-10 11:26:21 -07:00
LiveRangeEdit.cpp [CallSiteInfo] Handle bundles when updating call site info 2020-02-27 13:57:06 +01:00
LiveRangeShrink.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
LiveRangeUtils.h
LiveRegMatrix.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
LiveRegUnits.cpp [LiveRegUnits] Add phys_regs_and_masks iterator range (NFC). 2019-12-11 09:34:42 +00:00
LiveStacks.cpp Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC 2019-08-01 23:27:28 +00:00
LiveVariables.cpp [PHIElimination] Compile time optimization for huge functions. 2020-02-05 18:10:03 -05:00
LocalStackSlotAllocation.cpp [Alignment][NFC] Transition to MachineFrameInfo::getObjectAlign() 2020-04-01 14:08:28 +00:00
LoopTraversal.cpp
LowLevelType.cpp GlobalISel: Fix else after return 2020-01-09 17:37:52 -05:00
LowerEmuTLS.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
MBFIWrapper.cpp [MBFI] Move BranchFolding::MBFIWrapper to its own files. NFC. 2020-01-28 10:58:46 -08:00
MIRCanonicalizerPass.cpp [NFC] Fix some spelling mistakes to test pushing to GH. 2020-02-04 11:07:31 +00:00
MIRNamerPass.cpp [llvm] Fixing MIRVRegNamerUtils to properly handle 2+ MachineBasicBlocks. 2019-12-04 18:36:08 -05:00
MIRPrinter.cpp [MIR] Add comments to INLINEASM immediate flag MachineOperands 2020-04-16 13:46:14 +02:00
MIRPrintingPass.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
MIRVRegNamerUtils.cpp MIRVRegNamerUtils.h - remove unnecessary includes. NFC. 2020-04-20 15:59:39 +01:00
MIRVRegNamerUtils.h MIRVRegNamerUtils.h - remove unnecessary includes. NFC. 2020-04-20 15:59:39 +01:00
MachineBasicBlock.cpp Extend BasicBlock sections to allow specifying clusters of basic blocks in the same section. 2020-04-13 12:19:59 -07:00
MachineBlockFrequencyInfo.cpp [BFI] Fix missed BFI updates in MachineSink. 2020-02-21 09:50:54 -08:00
MachineBlockPlacement.cpp [CodeGen] Allow partial tail duplication in Machine Block Placement. 2020-04-11 12:20:31 -07:00
MachineBranchProbabilityInfo.cpp Add missing includes needed to prune LLVMContext.h include, NFC 2019-11-14 15:23:15 -08:00
MachineCSE.cpp [MachineCSE] Don't carry the wrong location when hoisting 2020-04-06 16:36:22 -07:00
MachineCombiner.cpp [PGO][PGSO] Instrument the code gen / target passes. 2019-12-09 12:42:59 -08:00
MachineCopyPropagation.cpp [MCP] Add stats for backward copy propagation. NFC. 2019-12-30 16:48:28 +08:00
MachineDebugify.cpp Don't accidentally create MachineFunctions in mir-debugify/mir-strip-debugify 2020-04-17 14:28:41 -07:00
MachineDominanceFrontier.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
MachineDominators.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
MachineFrameInfo.cpp [Alignment][NFC] Add DebugStr and operator* 2020-04-06 12:09:45 +00:00
MachineFunction.cpp Extend BasicBlock sections to allow specifying clusters of basic blocks in the same section. 2020-04-13 12:19:59 -07:00
MachineFunctionPass.cpp [NewPM] Port MachineModuleInfo to the new pass manager. 2019-09-30 17:54:50 +00:00
MachineFunctionPrinterPass.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
MachineInstr.cpp [MIR] Add comments to INLINEASM immediate flag MachineOperands 2020-04-16 13:46:14 +02:00
MachineInstrBundle.cpp CodeGen: Use Register in MachineInstrBuilder 2020-04-08 17:03:53 -04:00
MachineLICM.cpp [CallSiteInfo] Handle bundles when updating call site info 2020-02-27 13:57:06 +01:00
MachineLoopInfo.cpp Revert "Include static prof data when collecting loop BBs" 2020-03-24 09:41:16 -07:00
MachineLoopUtils.cpp [CodeGen] Fix a simple FIXME. NFC. 2020-04-09 10:54:03 +01:00
MachineModuleInfo.cpp Allow MachineFunction to obtain non-const Function (to enable MIR-level debugify) 2020-04-06 15:19:21 -07:00
MachineModuleInfoImpls.cpp
MachineOperand.cpp [Alignment][NFC] Provide tightened up functions in SelectionDAG, MachineFunction and MachineMemOperand 2020-03-30 13:03:27 +00:00
MachineOptimizationRemarkEmitter.cpp Make llvm::StringRef to std::string conversions explicit. 2020-01-28 23:25:25 +01:00
MachineOutliner.cpp fix to outline cfi instruction when can be grouped in a tail call 2020-04-17 22:26:34 -07:00
MachinePipeliner.cpp Provide operand indices to adjustSchedDependency 2020-04-17 11:08:44 +01:00
MachinePostDominators.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
MachineRegionInfo.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
MachineRegisterInfo.cpp CodeGen: Use Register in more places 2020-04-07 15:59:40 -04:00
MachineSSAUpdater.cpp CodeGen: Use Register in MachineSSAUpdater 2020-04-08 14:29:01 -04:00
MachineScheduler.cpp Add OffsetIsScalable to getMemOperandWithOffset 2020-02-18 15:53:29 +00:00
MachineSink.cpp [ARM] Mir test for machine sinking multiple def instructions. NFC 2020-04-16 20:58:14 +01:00
MachineSizeOpts.cpp [PGO][PGSO] Use IsColdXNthPercentile for sample PGO. 2020-03-05 09:54:54 -08:00
MachineStripDebug.cpp Don't accidentally create MachineFunctions in mir-debugify/mir-strip-debugify 2020-04-17 14:28:41 -07:00
MachineTraceMetrics.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
MachineVerifier.cpp [Statepoint] Add getters to StatepointOpers. 2020-04-15 14:31:42 +03:00
MacroFusion.cpp [NFC][MacroFusion] Adding the assertion if someone want to fuse more than 2 instructions 2019-12-10 03:10:21 +00:00
ModuloSchedule.cpp Add OffsetIsScalable to getMemOperandWithOffset 2020-02-18 15:53:29 +00:00
NonRelocatableStringpool.cpp [Dsymutil][Debuginfo][NFC] Reland: Refactor dsymutil to separate DWARF optimizing part. #2. 2020-01-08 14:15:31 +03:00
OptimizePHIs.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
PHIElimination.cpp [PHIElimination] Compile time optimization for huge functions. 2020-02-05 18:10:03 -05:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h
ParallelCG.cpp [Support] On Windows, ensure hardware_concurrency() extends to all CPU sockets and all NUMA groups 2020-02-14 10:24:22 -05:00
PatchableFunction.cpp [PatchableFunction] Use an empty DebugLoc 2020-02-01 14:12:06 -08:00
PeepholeOptimizer.cpp CodeGen: Convert some TII hooks to use Register 2020-04-03 14:52:54 -04:00
PostRAHazardRecognizer.cpp Replace wrongly deleted header banner, fix formatting 2019-11-14 10:21:42 -08:00
PostRASchedulerList.cpp [AntidepBreaker] Move AntiDepBreaker to include folder. 2020-04-14 11:40:57 -07:00
PreISelIntrinsicLowering.cpp [Alignement][NFC] Deprecate untyped CreateAlignedLoad 2020-01-23 13:34:32 +01:00
ProcessImplicitDefs.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
PrologEpilogInserter.cpp CodeGen: Use Register in TargetFrameLowering 2020-04-07 17:07:44 -04:00
PseudoSourceValue.cpp [llvm] Migrate llvm::make_unique to std::make_unique 2019-08-15 15:54:37 +00:00
RDFGraph.cpp Move RDF from Hexagon to Codegen 2020-03-17 12:43:14 -07:00
RDFLiveness.cpp Move RDF from Hexagon to Codegen 2020-03-17 12:43:14 -07:00
RDFRegisters.cpp Move RDF from Hexagon to Codegen 2020-03-17 12:43:14 -07:00
README.txt
ReachingDefAnalysis.cpp [RDA] Avoid full reprocessing of blocks in loops (NFCI) 2020-04-07 17:55:37 +02:00
RegAllocBase.cpp Move Spiller.h from lib/ directory path to include/CodeGen. NFC 2020-03-09 10:52:28 -07:00
RegAllocBase.h
RegAllocBasic.cpp Move Spiller.h from lib/ directory path to include/CodeGen. NFC 2020-03-09 10:52:28 -07:00
RegAllocFast.cpp [Alignment][NFC] Use more Align versions of various functions 2020-04-02 09:00:53 +00:00
RegAllocGreedy.cpp [RAGreedy] Fix minor typo in comment. NFC 2020-03-12 08:15:04 -07:00
RegAllocPBQP.cpp Move Spiller.h from lib/ directory path to include/CodeGen. NFC 2020-03-09 10:52:28 -07:00
RegUsageInfoCollector.cpp Reland [AArch64][DebugInfo] Do not recompute CalleeSavedStackSize (Take 2) 2019-10-29 16:13:07 +00:00
RegUsageInfoPropagate.cpp [NFC][RUIP] Small debug output refine 2020-03-24 03:29:45 +00:00
RegisterClassInfo.cpp RegisterClassInfo::computePSetLimit - assert that we actually find a register. 2020-01-15 12:18:12 +00:00
RegisterCoalescer.cpp RegisterCoalescer: Add LaneMask to debug printing 2020-02-10 12:34:33 -08:00
RegisterCoalescer.h
RegisterPressure.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
RegisterScavenging.cpp [Alignment][NFC] Transition to MachineFrameInfo::getObjectAlign() 2020-04-01 14:08:28 +00:00
RegisterUsageInfo.cpp
RenameIndependentSubregs.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
ResetMachineFunctionPass.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
SafeStack.cpp [llvm][NFC] CallSite removal from inliner-related files 2020-04-13 21:28:58 -07:00
SafeStackColoring.cpp
SafeStackColoring.h
SafeStackLayout.cpp
SafeStackLayout.h
ScalarizeMaskedMemIntrin.cpp Clean up usages of asserting vector getters in Type 2020-04-10 14:53:43 -07:00
ScheduleDAG.cpp
ScheduleDAGInstrs.cpp Let targets adjust physical output- and anti-deps 2020-04-21 13:45:03 +01:00
ScheduleDAGPrinter.cpp Make llvm::StringRef to std::string conversions explicit. 2020-01-28 23:25:25 +01:00
ScoreboardHazardRecognizer.cpp [MC] Widen the functional unit type from 32 to 64 bits. 2020-02-24 09:37:00 +01:00
ShadowStackGCLowering.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
ShrinkWrap.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
SjLjEHPrepare.cpp [VE] Target-specific bit size for sjljehprepare 2020-03-10 17:51:16 +01:00
SlotIndexes.cpp [LiveIntervals] Replace handleMoveIntoBundle 2020-04-16 19:58:19 +09:00
SpillPlacement.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
SpillPlacement.h
SplitKit.cpp Split LiveRangeCalc in LiveRangeCalc/LiveIntervalCalc. NFC 2020-04-10 11:26:21 -07:00
SplitKit.h Split LiveRangeCalc in LiveRangeCalc/LiveIntervalCalc. NFC 2020-04-10 11:26:21 -07:00
StackColoring.cpp [Alignment][NFC] Transition to MachineFrameInfo::getObjectAlign() 2020-04-01 14:08:28 +00:00
StackMapLivenessAnalysis.cpp Sink all InitializePasses.h includes 2019-11-13 16:34:37 -08:00
StackMaps.cpp [MC] Add MCStreamer::emitInt{8,16,32,64} 2020-02-29 09:40:21 -08:00
StackProtector.cpp [StackProtector] Catch direct out-of-bounds when checking address-takenness 2020-03-17 12:09:07 +00:00
StackSlotColoring.cpp [Alignment][NFC] Transition to MachineFrameInfo::getObjectAlign() 2020-04-01 14:08:28 +00:00
SwiftErrorValueTracking.cpp [CallSite removal][CodeGen] Use CallBase instead of ImmutableCallSite in SwiftErrorValueTracking. NFC 2020-04-13 00:19:27 -07:00
SwitchLoweringUtils.cpp [PGO][PGSO] TargetLowering/TargetTransformationInfo/SwitchLoweringUtils part. 2019-10-31 13:22:56 -07:00
TailDuplication.cpp [PGO][PGSO] Handle MBFIWrapper 2020-01-31 09:36:55 -08:00
TailDuplicator.cpp [CallSiteInfo] Handle bundles when updating call site info 2020-02-27 13:57:06 +01:00
TargetFrameLoweringImpl.cpp [CallSite removal][CodeGen] Use CallBase instead of ImmutableCallSite in TargetFrameLoweringInfo. NFC 2020-04-13 00:20:12 -07:00
TargetInstrInfo.cpp [MIR] Add comments to INLINEASM immediate flag MachineOperands 2020-04-16 13:46:14 +02:00
TargetLoweringBase.cpp [llvm][Codegen] Make `getVectorTypeBreakdownMVT` work with scalable types. 2020-04-10 00:48:27 +01:00
TargetLoweringObjectFileImpl.cpp [XCOFF][AIX] Fix getSymbol to return the correct qualname when necessary 2020-04-17 13:45:14 +00:00
TargetOptionsImpl.cpp Reland D73534: [DebugInfo] Enable the debug entry values feature by default 2020-03-19 13:57:30 +01:00
TargetPassConfig.cpp Add -debugify-and-strip-all to add debug info before a pass and remove it after 2020-04-10 16:36:07 -07:00
TargetRegisterInfo.cpp CodeGen: More conversions to use Register 2020-04-07 18:54:36 -04:00
TargetSchedule.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
TargetSubtargetInfo.cpp [Scheduling][ARM] Consistently enable PostRA Machine scheduling 2019-11-05 10:44:55 +00:00
TwoAddressInstructionPass.cpp CodeGen: Use Register in MachineBasicBlock 2020-04-08 12:10:58 -04:00
TypePromotion.cpp [ARM] Fix non-determenistic behaviour 2020-02-06 09:21:13 +00:00
UnreachableBlockElim.cpp [CallSiteInfo] Handle bundles when updating call site info 2020-02-27 13:57:06 +01:00
ValueTypes.cpp [SVE][SelectionDAG] Fix dumping of EVTs to use correct API for element count. 2020-03-30 16:47:53 -07:00
VirtRegMap.cpp [Alignment][NFC] Use more Align versions of various functions 2020-04-02 09:00:53 +00:00
WasmEHPrepare.cpp [WebAssembly] Fix a sanitizer error in WasmEHPrepare 2020-04-04 09:57:07 -07:00
WinEHPrepare.cpp [CallSite removal][CodeGen] Use CallBase instead of ImmutableCallSite in WinEHPrepare. NFC 2020-04-13 00:19:27 -07:00
XRayInstrumentation.cpp [CallSiteInfo] Handle bundles when updating call site info 2020-02-27 13:57:06 +01:00

README.txt

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %noreg, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side
effects).  Once this is in place, it would be even better to have tblgen
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStacks analysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.