..
32-bit-local-address-space.ll
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README
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add-debug.ll
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add.ll
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add_i64.ll
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address-space.ll
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and.ll
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anyext.ll
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array-ptr-calc-i32.ll
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array-ptr-calc-i64.ll
AMDGPU: Avoid using 64-bit shift for i64 (shl x, 32)
2015-07-14 18:20:33 +00:00
atomic_cmp_swap_local.ll
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atomic_load_add.ll
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atomic_load_sub.ll
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basic-branch.ll
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basic-loop.ll
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bfe_uint.ll
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bfi_int.ll
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big_alu.ll
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bitcast.ll
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bswap.ll
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build_vector.ll
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call.ll
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call_fs.ll
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cayman-loop-bug.ll
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cf-stack-bug.ll
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cf_end.ll
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cgp-addressing-modes-flat.ll
AMDGPU: Assume SMRD access for constant address space
2015-08-07 20:18:34 +00:00
cgp-addressing-modes.ll
AMDGPU: Assume SMRD access for constant address space
2015-08-07 20:18:34 +00:00
coalescer_remat.ll
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codegen-prepare-addrmode-sext.ll
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combine_vloads.ll
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commute-compares.ll
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commute-shifts.ll
AMDGPU: really don't commute REV opcodes if the target variant doesn't exist
2015-06-26 20:29:10 +00:00
commute_modifiers.ll
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complex-folding.ll
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concat_vectors.ll
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copy-illegal-type.ll
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copy-to-reg.ll
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ctlz_zero_undef.ll
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ctpop.ll
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ctpop64.ll
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cttz_zero_undef.ll
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cvt_f32_ubyte.ll
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cvt_flr_i32_f32.ll
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cvt_rpi_i32_f32.ll
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dagcombiner-bug-illegal-vec4-int-to-fp.ll
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debug.ll
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default-fp-mode.ll
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disconnected-predset-break-bug.ll
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dot4-folding.ll
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ds-negative-offset-addressing-mode-loop.ll
AMDGPU/SI: Add debugging subtarget feature for DS offsets
2015-07-06 16:01:58 +00:00
ds_read2.ll
AMDGPU/SI: Fix read2 merging into a super register.
2015-07-14 17:57:36 +00:00
ds_read2_offset_order.ll
AMDGPU/SI: Fix read2 merging into a super register.
2015-07-14 17:57:36 +00:00
ds_read2_superreg.ll
AMDGPU/SI: Fix read2 merging into a super register.
2015-07-14 17:57:36 +00:00
ds_read2st64.ll
AMDGPU/SI: Fix read2 merging into a super register.
2015-07-14 17:57:36 +00:00
ds_write2.ll
AMDGPU/SI: Fix read2 merging into a super register.
2015-07-14 17:57:36 +00:00
ds_write2st64.ll
AMDGPU/SI: Fix read2 merging into a super register.
2015-07-14 17:57:36 +00:00
elf.ll
AMDGPU/SI: Set ELF OS/ABI to ELFOSABI_AMDGPU_HSA
2015-06-26 21:15:11 +00:00
elf.r600.ll
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empty-function.ll
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endcf-loop-header.ll
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extload-private.ll
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extload.ll
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extract_vector_elt_i16.ll
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fabs.f64.ll
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fabs.ll
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fadd.ll
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fadd64.ll
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fceil.ll
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fceil64.ll
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fcmp-cnd.ll
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fcmp-cnde-int-args.ll
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fcmp.ll
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fcmp64.ll
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fconst64.ll
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fcopysign.f32.ll
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fcopysign.f64.ll
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fdiv.f64.ll
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fdiv.ll
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fetch-limits.r600.ll
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fetch-limits.r700+.ll
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ffloor.f64.ll
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ffloor.ll
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flat-address-space.ll
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floor.ll
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fma-combine.ll
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fma.f64.ll
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fma.ll
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fmad.ll
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fmax.ll
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fmax3.f64.ll
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fmax3.ll
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fmax_legacy.f64.ll
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fmax_legacy.ll
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fmaxnum.f64.ll
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fmaxnum.ll
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fmin.ll
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fmin3.ll
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fmin_legacy.f64.ll
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fmin_legacy.ll
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fminnum.f64.ll
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fminnum.ll
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fmul-2-combine-multi-use.ll
Only do fmul (fadd x, x), c combine if the fadd only has one use
2015-07-17 01:14:35 +00:00
fmul.ll
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fmul64.ll
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fmuladd.ll
AMDGPU/SI: Select mad patterns to v_mac_f32
2015-07-13 15:47:57 +00:00
fnearbyint.ll
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fneg-fabs.f64.ll
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fneg-fabs.ll
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fneg.f64.ll
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fneg.ll
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fp-classify.ll
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fp16_to_fp.ll
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fp32_to_fp16.ll
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fp_to_sint.f64.ll
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fp_to_sint.ll
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fp_to_uint.f64.ll
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fp_to_uint.ll
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fpext.ll
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fptrunc.ll
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frem.ll
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fsqrt.ll
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fsub.ll
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fsub64.ll
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ftrunc.f64.ll
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ftrunc.ll
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gep-address-space.ll
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global-directive.ll
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global-extload-i1.ll
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global-extload-i8.ll
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global-extload-i16.ll
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global-extload-i32.ll
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global-zero-initializer.ll
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global_atomics.ll
AMDGPU/SI: Add VI patterns to select FLAT instructions for global memory ops
2015-07-20 14:28:41 +00:00
gv-const-addrspace-fail.ll
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gv-const-addrspace.ll
AMDGPU: don't match vgpr loads for constant loads
2015-07-27 18:16:08 +00:00
half.ll
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hsa.ll
AMDPGU/SI: Use correct resource descriptors for VI on HSA
2015-06-26 21:58:42 +00:00
i1-copy-implicit-def.ll
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i1-copy-phi.ll
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i8-to-double-to-float.ll
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icmp-select-sete-reverse-args.ll
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icmp64.ll
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image-attributes.ll
AMDGPU: Add pass to lower OpenCL image and sampler arguments.
2015-08-07 23:19:30 +00:00
image-resource-id.ll
AMDGPU: Add pass to lower OpenCL image and sampler arguments.
2015-08-07 23:19:30 +00:00
imm.ll
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indirect-addressing-si.ll
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indirect-private-64.ll
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infinite-loop-evergreen.ll
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infinite-loop.ll
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inline-asm.ll
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inline-calls.ll
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input-mods.ll
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insert_subreg.ll
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insert_vector_elt.ll
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invariant-load-no-alias-store.ll
DAGCombiner: Assume invariant load cannot alias a store
2015-07-10 22:17:40 +00:00
jump-address.ll
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kcache-fold.ll
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kernel-args.ll
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large-alloca.ll
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large-constant-initializer.ll
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lds-initializer.ll
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lds-oqap-crash.ll
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lds-output-queue.ll
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lds-size.ll
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lds-zero-initializer.ll
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legalizedag-bug-expand-setcc.ll
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lit.local.cfg
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literals.ll
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llvm.AMDGPU.abs.ll
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llvm.AMDGPU.barrier.global.ll
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llvm.AMDGPU.barrier.local.ll
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llvm.AMDGPU.bfe.i32.ll
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llvm.AMDGPU.bfe.u32.ll
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llvm.AMDGPU.bfi.ll
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llvm.AMDGPU.bfm.ll
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llvm.AMDGPU.brev.ll
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llvm.AMDGPU.clamp.ll
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llvm.AMDGPU.class.ll
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llvm.AMDGPU.cube.ll
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llvm.AMDGPU.cvt_f32_ubyte.ll
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llvm.AMDGPU.div_fixup.ll
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llvm.AMDGPU.div_fmas.ll
AMDGPU/SI: Fix extra space when printing v_div_fmas_*
2015-06-28 18:16:14 +00:00
llvm.AMDGPU.div_scale.ll
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llvm.AMDGPU.flbit.i32.ll
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llvm.AMDGPU.fract.f64.ll
AMDGPU/SI: Fix the V_FRACT_F64 SI bug workaround
2015-07-27 11:37:42 +00:00
llvm.AMDGPU.fract.ll
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llvm.AMDGPU.imad24.ll
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llvm.AMDGPU.imax.ll
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llvm.AMDGPU.imin.ll
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llvm.AMDGPU.imul24.ll
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llvm.AMDGPU.kill.ll
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llvm.AMDGPU.ldexp.ll
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llvm.AMDGPU.legacy.rsq.ll
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llvm.AMDGPU.mul.ll
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llvm.AMDGPU.rcp.f64.ll
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llvm.AMDGPU.rcp.ll
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llvm.AMDGPU.rsq.clamped.f64.ll
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llvm.AMDGPU.rsq.clamped.ll
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llvm.AMDGPU.rsq.ll
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llvm.AMDGPU.tex.ll
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llvm.AMDGPU.trig_preop.ll
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llvm.AMDGPU.trunc.ll
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llvm.AMDGPU.umad24.ll
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llvm.AMDGPU.umax.ll
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llvm.AMDGPU.umin.ll
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llvm.AMDGPU.umul24.ll
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llvm.SI.fs.interp.ll
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llvm.SI.gather4.ll
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llvm.SI.getlod.ll
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llvm.SI.image.ll
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llvm.SI.image.sample.ll
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llvm.SI.image.sample.o.ll
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llvm.SI.imageload.ll
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llvm.SI.load.dword.ll
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llvm.SI.resinfo.ll
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llvm.SI.sample-masked.ll
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llvm.SI.sample.ll
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llvm.SI.sampled.ll
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llvm.SI.sendmsg-m0.ll
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llvm.SI.sendmsg.ll
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llvm.SI.tbuffer.store.ll
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llvm.SI.tid.ll
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llvm.amdgpu.dp4.ll
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llvm.amdgpu.kilp.ll
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llvm.amdgpu.lrp.ll
AMDGPU/SI: Select mad patterns to v_mac_f32
2015-07-13 15:47:57 +00:00
llvm.cos.ll
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llvm.dbg.value.ll
AMDGPU: Fix assert on dbg_value instructions
2015-08-12 09:04:44 +00:00
llvm.exp2.ll
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llvm.log2.ll
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llvm.memcpy.ll
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llvm.pow.ll
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llvm.rint.f64.ll
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llvm.rint.ll
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llvm.round.f64.ll
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llvm.round.ll
AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
2015-07-14 14:15:03 +00:00
llvm.sin.ll
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llvm.sqrt.ll
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load-i1.ll
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load-input-fold.ll
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load.ll
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load.vec.ll
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load64.ll
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local-64.ll
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local-atomics.ll
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local-atomics64.ll
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local-memory-two-objects.ll
Fix "the the" in comments.
2015-06-19 01:53:21 +00:00
local-memory.ll
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loop-address.ll
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loop-idiom.ll
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lshl.ll
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lshr.ll
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m0-spill.ll
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mad-combine.ll
AMDGPU/SI: Select mad patterns to v_mac_f32
2015-07-13 15:47:57 +00:00
mad-sub.ll
AMDGPU/SI: Select mad patterns to v_mac_f32
2015-07-13 15:47:57 +00:00
mad_int24.ll
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mad_uint24.ll
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madak.ll
AMDGPU/SI: Select mad patterns to v_mac_f32
2015-07-13 15:47:57 +00:00
madmk.ll
AMDGPU/SI: Select mad patterns to v_mac_f32
2015-07-13 15:47:57 +00:00
max-literals.ll
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max.ll
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max3.ll
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merge-stores.ll
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min.ll
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min3.ll
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missing-store.ll
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mubuf.ll
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mul.ll
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mul_int24.ll
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mul_uint24.ll
AMDGPU: Avoid using 64-bit shift for i64 (shl x, 32)
2015-07-14 18:20:33 +00:00
mulhu.ll
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no-initializer-constant-addrspace.ll
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no-shrink-extloads.ll
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operand-folding.ll
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operand-spacing.ll
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or.ll
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packetizer.ll
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parallelandifcollapse.ll
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parallelorifcollapse.ll
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predicate-dp4.ll
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predicates.ll
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private-memory-atomics.ll
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private-memory-broken.ll
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private-memory.ll
AMDPGU/SI: Negative offsets aren't allowed in MUBUF's vaddr operand
2015-07-16 19:40:09 +00:00
promote-alloca-bitcast-function.ll
AMDGPU: Fix crash if called function is a bitcast
2015-07-28 18:29:14 +00:00
promote-alloca-stored-pointer-value.ll
AMDGPU: Don't try to use LDS/vector for private if pointer value stored
2015-07-28 18:47:00 +00:00
pv-packing.ll
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pv.ll
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r600-encoding.ll
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r600-export-fix.ll
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r600-infinite-loop-bug-while-reorganizing-vector.ll
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r600cfg.ll
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reciprocal.ll
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register-count-comments.ll
AMDGPU/SI: Fix printing useless info with amdhsa
2015-08-15 00:12:39 +00:00
reorder-stores.ll
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rotl.i64.ll
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rotl.ll
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rotr.i64.ll
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rotr.ll
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rsq.ll
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rv7x0_count3.ll
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s_movk_i32.ll
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saddo.ll
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salu-to-valu.ll
AMDGPU: Assume SMRD access for constant address space
2015-08-07 20:18:34 +00:00
sampler-resource-id.ll
AMDGPU: Add pass to lower OpenCL image and sampler arguments.
2015-08-07 23:19:30 +00:00
scalar_to_vector.ll
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schedule-fs-loop-nested-if.ll
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schedule-fs-loop-nested.ll
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schedule-fs-loop.ll
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schedule-global-loads.ll
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schedule-if-2.ll
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schedule-if.ll
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schedule-kernel-arg-loads.ll
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schedule-vs-if-nested-loop-failure.ll
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schedule-vs-if-nested-loop.ll
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scratch-buffer.ll
AMDPGU/SI: Negative offsets aren't allowed in MUBUF's vaddr operand
2015-07-16 19:40:09 +00:00
sdiv.ll
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sdivrem24.ll
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sdivrem64.ll
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select-i1.ll
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select-vectors.ll
AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
2015-07-14 14:15:03 +00:00
select.ll
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select64.ll
AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
2015-07-14 14:15:03 +00:00
selectcc-cnd.ll
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selectcc-cnde-int.ll
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selectcc-icmp-select-float.ll
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selectcc-opt.ll
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selectcc.ll
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set-dx10.ll
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setcc-equivalent.ll
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setcc-opt.ll
AMDGPU/SI: Better handle s_wait insertion
2015-08-21 22:47:27 +00:00
setcc.ll
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setcc64.ll
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seto.ll
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setuo.ll
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sext-eliminate.ll
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sext-in-reg.ll
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sgpr-control-flow.ll
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sgpr-copy-duplicate-operand.ll
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sgpr-copy.ll
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shared-op-cycle.ll
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shl.ll
AMDGPU: Avoid using 64-bit shift for i64 (shl x, 32)
2015-07-14 18:20:33 +00:00
shl_add_constant.ll
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shl_add_ptr.ll
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si-annotate-cf-assertion.ll
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si-annotate-cf.ll
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si-instr-info-correct-implicit-operands.ll
AMDGPU/SI: Add implicit register operands in the correct order.
2015-07-31 23:30:09 +00:00
si-lod-bias.ll
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si-sgpr-spill.ll
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si-spill-cf.ll
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si-triv-disjoint-mem-access.ll
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si-vector-hang.ll
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sign_extend.ll
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simplify-demanded-bits-build-pair.ll
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sint_to_fp.f64.ll
AMDGPU: Improve accuracy of instruction rates for some FP instructions
2015-08-22 00:50:41 +00:00
sint_to_fp.ll
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smrd.ll
AMDGPU/SI: Add support for 32-bit immediate SMRD offsets on CI
2015-08-06 19:28:38 +00:00
split-scalar-i64-add.ll
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sra.ll
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srem.ll
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srl.ll
AMDGPU: Avoid using 64-bit shift for i64 (shl x, 32)
2015-07-14 18:20:33 +00:00
ssubo.ll
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store-barrier.ll
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store-v3i32.ll
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store-v3i64.ll
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store-vector-ptrs.ll
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store.ll
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store.r600.ll
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structurize.ll
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structurize1.ll
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sub.ll
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subreg-coalescer-crash.ll
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subreg-coalescer-undef-use.ll
Test for specific output in lit test
2015-07-01 22:34:59 +00:00
subreg-eliminate-dead.ll
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swizzle-export.ll
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tex-clause-antidep.ll
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texture-input-merge.ll
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trunc-cmp-constant.ll
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trunc-store-f64-to-f16.ll
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trunc-store-i1.ll
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trunc-store.ll
AMDGPU: Fix v16i32 to v16i8 truncstore
2015-07-31 04:12:04 +00:00
trunc-vector-store-assertion-failure.ll
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trunc.ll
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tti-unroll-prefs.ll
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uaddo.ll
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udiv.ll
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udivrem.ll
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udivrem24.ll
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udivrem64.ll
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uint_to_fp.f64.ll
AMDGPU: Improve accuracy of instruction rates for some FP instructions
2015-08-22 00:50:41 +00:00
uint_to_fp.ll
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unaligned-load-store.ll
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unhandled-loop-condition-assertion.ll
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unroll.ll
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unsupported-cc.ll
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urecip.ll
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urem.ll
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use-sgpr-multiple-times.ll
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usubo.ll
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v1i64-kernel-arg.ll
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v_cndmask.ll
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v_mac.ll
AMDGPU/SI: Select mad patterns to v_mac_f32
2015-07-13 15:47:57 +00:00
valu-i1.ll
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vector-alloca.ll
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vertex-fetch-encoding.ll
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vop-shrink.ll
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vselect.ll
AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
2015-07-14 14:15:03 +00:00
vselect64.ll
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vtx-fetch-branch.ll
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vtx-schedule.ll
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wait.ll
AMDGPU/SI: Better handle s_wait insertion
2015-08-21 22:47:27 +00:00
work-item-intrinsics.ll
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wrong-transalu-pos-fix.ll
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xor.ll
AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
2015-07-14 14:15:03 +00:00
zero_extend.ll
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