forked from OSchip/llvm-project
518 lines
17 KiB
TableGen
518 lines
17 KiB
TableGen
//==- SystemZInstrSystem.td - SystemZ system instructions -*- tblgen-*-----==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// The instructions in this file implement SystemZ system-level instructions.
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// Most of these instructions are privileged or semi-privileged. They are
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// not used for code generation, but are provided for use with the assembler
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// and disassembler only.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Program-Status Word Instructions.
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//===----------------------------------------------------------------------===//
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// Extract PSW.
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let hasSideEffects = 1, Uses = [CC] in
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def EPSW : InherentDualRRE<"epsw", 0xB98D, GR32>;
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// Load PSW (extended).
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let hasSideEffects = 1, Defs = [CC], mayLoad = 1 in {
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def LPSW : SideEffectUnaryS<"lpsw", 0x8200, null_frag, 8>;
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def LPSWE : SideEffectUnaryS<"lpswe", 0xB2B2, null_frag, 16>;
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}
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// Insert PSW key.
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let Uses = [R2L], Defs = [R2L] in
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def IPK : SideEffectInherentS<"ipk", 0xB20B, null_frag>;
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// Set PSW key from address.
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let hasSideEffects = 1 in
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def SPKA : SideEffectAddressS<"spka", 0xB20A, null_frag>;
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// Set system mask.
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let hasSideEffects = 1, mayLoad = 1 in
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def SSM : SideEffectUnaryS<"ssm", 0x8000, null_frag, 1>;
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// Store then AND/OR system mask.
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let hasSideEffects = 1 in {
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def STNSM : StoreSI<"stnsm", 0xAC, null_frag, imm32zx8>;
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def STOSM : StoreSI<"stosm", 0xAD, null_frag, imm32zx8>;
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}
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// Insert address space control.
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let hasSideEffects = 1 in
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def IAC : InherentRRE<"iac", 0xB224, GR32, null_frag>;
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// Set address space control (fast).
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let hasSideEffects = 1 in {
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def SAC : SideEffectAddressS<"sac", 0xB219, null_frag>;
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def SACF : SideEffectAddressS<"sacf", 0xB279, null_frag>;
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}
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//===----------------------------------------------------------------------===//
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// Control Register Instructions.
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//===----------------------------------------------------------------------===//
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// Load control.
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def LCTL : LoadMultipleRS<"lctl", 0xB7, CR64>;
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def LCTLG : LoadMultipleRSY<"lctlg", 0xEB2F, CR64>;
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// Store control.
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def STCTL : StoreMultipleRS<"stctl", 0xB6, CR64>;
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def STCTG : StoreMultipleRSY<"stctg", 0xEB25, CR64>;
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// Extract primary ASN (and instance).
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let hasSideEffects = 1 in {
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def EPAR : InherentRRE<"epar", 0xB226, GR32, null_frag>;
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def EPAIR : InherentRRE<"epair", 0xB99A, GR64, null_frag>;
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}
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// Extract secondary ASN (and instance).
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let hasSideEffects = 1 in {
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def ESAR : InherentRRE<"esar", 0xB227, GR32, null_frag>;
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def ESAIR : InherentRRE<"esair", 0xB99B, GR64, null_frag>;
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}
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// Set secondary ASN (and instance).
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let hasSideEffects = 1 in {
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def SSAR : SideEffectUnaryRRE<"ssar", 0xB225, GR32, null_frag>;
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def SSAIR : SideEffectUnaryRRE<"ssair", 0xB99F, GR64, null_frag>;
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}
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// Extract and set extended authority.
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let hasSideEffects = 1 in
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def ESEA : UnaryTiedRRE<"esea", 0xB99D, GR32>;
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//===----------------------------------------------------------------------===//
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// Prefix-Register Instructions.
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//===----------------------------------------------------------------------===//
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// Set prefix.
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let hasSideEffects = 1 in
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def SPX : SideEffectUnaryS<"spx", 0xB210, null_frag, 4>;
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// Store prefix.
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let hasSideEffects = 1 in
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def STPX : StoreInherentS<"stpx", 0xB211, null_frag, 4>;
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//===----------------------------------------------------------------------===//
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// Storage-Key and Real Memory Instructions.
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//===----------------------------------------------------------------------===//
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// Insert storage key extended.
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let hasSideEffects = 1 in
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def ISKE : BinaryRRE<"iske", 0xB229, null_frag, GR32, GR64>;
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// Insert virtual storage key.
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let hasSideEffects = 1 in
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def IVSK : BinaryRRE<"ivsk", 0xB223, null_frag, GR32, GR64>;
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// Set storage key extended.
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let hasSideEffects = 1, Defs = [CC] in
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defm SSKE : SideEffectTernaryRRFcOpt<"sske", 0xB22B, GR32, GR64>;
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// Reset reference bit extended.
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let hasSideEffects = 1, Defs = [CC] in
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def RRBE : SideEffectBinaryRRE<"rrbe", 0xB22A, GR32, GR64>;
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// Reset reference bits multiple.
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let Predicates = [FeatureResetReferenceBitsMultiple], hasSideEffects = 1 in
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def RRBM : UnaryRRE<"rrbm", 0xB9AE, null_frag, GR64, GR64>;
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// Perform frame management function.
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let hasSideEffects = 1 in
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def PFMF : SideEffectBinaryMemRRE<"pfmf", 0xB9AF, GR32, GR64>;
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// Test block.
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let hasSideEffects = 1, mayStore = 1, Uses = [R0D], Defs = [R0D, CC] in
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def TB : SideEffectBinaryRRE<"tb", 0xB22C, GR64, GR64>;
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// Page in / out.
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let mayLoad = 1, mayStore = 1, Defs = [CC] in {
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def PGIN : SideEffectBinaryRRE<"pgin", 0xB22E, GR64, GR64>;
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def PGOUT : SideEffectBinaryRRE<"pgout", 0xB22F, GR64, GR64>;
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}
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//===----------------------------------------------------------------------===//
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// Dynamic-Address-Translation Instructions.
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//===----------------------------------------------------------------------===//
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// Invalidate page table entry.
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let hasSideEffects = 1 in
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defm IPTE : SideEffectQuaternaryRRFaOptOpt<"ipte", 0xB221, GR64, GR32, GR32>;
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// Invalidate DAT table entry.
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let hasSideEffects = 1 in
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defm IDTE : SideEffectQuaternaryRRFbOpt<"idte", 0xB98E, GR64, GR64, GR64>;
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// Compare and replace DAT table entry.
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let Predicates = [FeatureEnhancedDAT2], hasSideEffects = 1, Defs = [CC] in
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defm CRDTE : SideEffectQuaternaryRRFbOpt<"crdte", 0xB98F, GR128, GR128, GR64>;
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// Purge TLB.
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let hasSideEffects = 1 in
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def PTLB : SideEffectInherentS<"ptlb", 0xB20D, null_frag>;
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// Compare and swap and purge.
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let hasSideEffects = 1, Defs = [CC] in {
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def CSP : CmpSwapRRE<"csp", 0xB250, GR128, GR64>;
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def CSPG : CmpSwapRRE<"cspg", 0xB98A, GR128, GR64>;
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}
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// Load page-table-entry address.
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let hasSideEffects = 1, Defs = [CC] in
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def LPTEA : TernaryRRFb<"lptea", 0xB9AA, GR64, GR64, GR64>;
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// Load real address.
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let hasSideEffects = 1, Defs = [CC] in {
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defm LRA : LoadAddressRXPair<"lra", 0xB1, 0xE313, null_frag>;
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def LRAG : LoadAddressRXY<"lrag", 0xE303, null_frag, laaddr20pair>;
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}
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// Store real address.
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def STRAG : StoreSSE<"strag", 0xE502>;
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// Load using real address.
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let mayLoad = 1 in {
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def LURA : UnaryRRE<"lura", 0xB24B, null_frag, GR32, GR64>;
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def LURAG : UnaryRRE<"lurag", 0xB905, null_frag, GR64, GR64>;
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}
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// Store using real address.
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let mayStore = 1 in {
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def STURA : SideEffectBinaryRRE<"stura", 0xB246, GR32, GR64>;
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def STURG : SideEffectBinaryRRE<"sturg", 0xB925, GR64, GR64>;
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}
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// Test protection.
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let hasSideEffects = 1, Defs = [CC] in
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def TPROT : SideEffectBinarySSE<"tprot", 0xE501>;
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//===----------------------------------------------------------------------===//
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// Memory-move Instructions.
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//===----------------------------------------------------------------------===//
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// Move with key.
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let mayLoad = 1, mayStore = 1, Defs = [CC] in
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def MVCK : MemoryBinarySSd<"mvck", 0xD9, GR64>;
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// Move to primary / secondary.
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let mayLoad = 1, mayStore = 1, Defs = [CC] in {
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def MVCP : MemoryBinarySSd<"mvcp", 0xDA, GR64>;
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def MVCS : MemoryBinarySSd<"mvcs", 0xDB, GR64>;
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}
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// Move with source / destination key.
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let mayLoad = 1, mayStore = 1, Uses = [R0L, R1L] in {
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def MVCSK : SideEffectBinarySSE<"mvcsk", 0xE50E>;
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def MVCDK : SideEffectBinarySSE<"mvcdk", 0xE50F>;
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}
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// Move with optional specifications.
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let mayLoad = 1, mayStore = 1, Uses = [R0L] in
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def MVCOS : SideEffectTernarySSF<"mvcos", 0xC80, GR64>;
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// Move page.
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let mayLoad = 1, mayStore = 1, Uses = [R0L], Defs = [CC] in
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def MVPG : SideEffectBinaryRRE<"mvpg", 0xB254, GR64, GR64>;
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//===----------------------------------------------------------------------===//
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// Address-Space Instructions.
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//===----------------------------------------------------------------------===//
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// Load address space parameters.
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let hasSideEffects = 1, Defs = [CC] in
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def LASP : SideEffectBinarySSE<"lasp", 0xE500>;
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// Purge ALB.
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let hasSideEffects = 1 in
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def PALB : SideEffectInherentRRE<"palb", 0xB248>;
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// Program call.
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let hasSideEffects = 1 in
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def PC : SideEffectAddressS<"pc", 0xB218, null_frag>;
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// Program return.
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let hasSideEffects = 1, Defs = [CC] in
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def PR : SideEffectInherentE<"pr", 0x0101>;
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// Program transfer (with instance).
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let hasSideEffects = 1 in {
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def PT : SideEffectBinaryRRE<"pt", 0xB228, GR32, GR64>;
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def PTI : SideEffectBinaryRRE<"pti", 0xB99E, GR64, GR64>;
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}
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// Resume program.
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let hasSideEffects = 1, Defs = [CC] in
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def RP : SideEffectAddressS<"rp", 0xB277, null_frag>;
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// Branch in subspace group.
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let hasSideEffects = 1 in
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def BSG : UnaryRRE<"bsg", 0xB258, null_frag, GR64, GR64>;
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// Branch and set authority.
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let hasSideEffects = 1 in
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def BSA : UnaryRRE<"bsa", 0xB25A, null_frag, GR64, GR64>;
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// Test access.
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let Defs = [CC] in
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def TAR : SideEffectBinaryRRE<"tar", 0xB24C, AR32, GR32>;
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//===----------------------------------------------------------------------===//
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// Linkage-Stack Instructions.
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//===----------------------------------------------------------------------===//
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// Branch and stack.
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let hasSideEffects = 1 in
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def BAKR : SideEffectBinaryRRE<"bakr", 0xB240, GR64, GR64>;
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// Extract stacked registers.
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let hasSideEffects = 1 in {
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def EREG : SideEffectBinaryRRE<"ereg", 0xB249, GR32, GR32>;
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def EREGG : SideEffectBinaryRRE<"eregg", 0xB90E, GR64, GR64>;
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}
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// Extract stacked state.
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let hasSideEffects = 1, Defs = [CC] in
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def ESTA : UnaryRRE<"esta", 0xB24A, null_frag, GR128, GR32>;
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// Modify stacked state.
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let hasSideEffects = 1 in
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def MSTA : SideEffectUnaryRRE<"msta", 0xB247, GR128, null_frag>;
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//===----------------------------------------------------------------------===//
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// Time-Related Instructions.
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//===----------------------------------------------------------------------===//
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// Perform timing facility function.
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let hasSideEffects = 1, mayLoad = 1, Uses = [R0L, R1D], Defs = [CC] in
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def PTFF : SideEffectInherentE<"ptff", 0x0104>;
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// Set clock.
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let hasSideEffects = 1, Defs = [CC] in
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def SCK : SideEffectUnaryS<"sck", 0xB204, null_frag, 8>;
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// Set clock programmable field.
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let hasSideEffects = 1, Uses = [R0L] in
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def SCKPF : SideEffectInherentE<"sckpf", 0x0107>;
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// Set clock comparator.
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let hasSideEffects = 1 in
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def SCKC : SideEffectUnaryS<"sckc", 0xB206, null_frag, 8>;
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// Set CPU timer.
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let hasSideEffects = 1 in
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def SPT : SideEffectUnaryS<"spt", 0xB208, null_frag, 8>;
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// Store clock (fast / extended).
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let hasSideEffects = 1, Defs = [CC] in {
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def STCK : StoreInherentS<"stck", 0xB205, null_frag, 8>;
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def STCKF : StoreInherentS<"stckf", 0xB27C, null_frag, 8>;
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def STCKE : StoreInherentS<"stcke", 0xB278, null_frag, 16>;
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}
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// Store clock comparator.
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let hasSideEffects = 1 in
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def STCKC : StoreInherentS<"stckc", 0xB207, null_frag, 8>;
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// Store CPU timer.
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let hasSideEffects = 1 in
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def STPT : StoreInherentS<"stpt", 0xB209, null_frag, 8>;
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//===----------------------------------------------------------------------===//
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// CPU-Related Instructions.
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//===----------------------------------------------------------------------===//
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// Store CPU address.
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let hasSideEffects = 1 in
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def STAP : StoreInherentS<"stap", 0xB212, null_frag, 2>;
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// Store CPU ID.
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let hasSideEffects = 1 in
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def STIDP : StoreInherentS<"stidp", 0xB202, null_frag, 8>;
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// Store system information.
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let hasSideEffects = 1, Uses = [R0L, R1L], Defs = [R0L, CC] in
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def STSI : StoreInherentS<"stsi", 0xB27D, null_frag, 0>;
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// Store facility list.
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let hasSideEffects = 1 in
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def STFL : StoreInherentS<"stfl", 0xB2B1, null_frag, 4>;
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// Store facility list extended.
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let hasSideEffects = 1, Uses = [R0D], Defs = [R0D, CC] in
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def STFLE : StoreInherentS<"stfle", 0xB2B0, null_frag, 0>;
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// Extract CPU attribute.
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let hasSideEffects = 1 in
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def ECAG : BinaryRSY<"ecag", 0xEB4C, null_frag, GR64>;
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// Extract CPU time.
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let hasSideEffects = 1, mayLoad = 1, Defs = [R0D, R1D] in
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def ECTG : SideEffectTernarySSF<"ectg", 0xC81, GR64>;
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// Perform topology function.
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let hasSideEffects = 1 in
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def PTF : UnaryTiedRRE<"ptf", 0xB9A2, GR64>;
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// Perform cryptographic key management operation.
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let Predicates = [FeatureMessageSecurityAssist3],
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hasSideEffects = 1, Uses = [R0L, R1D] in
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def PCKMO : SideEffectInherentRRE<"pckmo", 0xB928>;
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//===----------------------------------------------------------------------===//
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// Miscellaneous Instructions.
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//===----------------------------------------------------------------------===//
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// Supervisor call.
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let hasSideEffects = 1, isCall = 1, Defs = [CC] in
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def SVC : SideEffectUnaryI<"svc", 0x0A, imm32zx8>;
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// Monitor call.
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let hasSideEffects = 1, isCall = 1 in
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def MC : SideEffectBinarySI<"mc", 0xAF, imm32zx8>;
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// Diagnose.
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let hasSideEffects = 1, isCall = 1 in
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def DIAG : SideEffectTernaryRS<"diag", 0x83, GR32, GR32>;
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// Trace.
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let hasSideEffects = 1, mayLoad = 1 in {
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def TRACE : SideEffectTernaryRS<"trace", 0x99, GR32, GR32>;
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def TRACG : SideEffectTernaryRSY<"tracg", 0xEB0F, GR64, GR64>;
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}
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// Trap.
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let hasSideEffects = 1 in {
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def TRAP2 : SideEffectInherentE<"trap2", 0x01FF>;
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def TRAP4 : SideEffectAddressS<"trap4", 0xB2FF, null_frag>;
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}
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// Signal processor.
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let hasSideEffects = 1, Defs = [CC] in
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def SIGP : SideEffectTernaryRS<"sigp", 0xAE, GR64, GR64>;
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// Signal adapter.
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let hasSideEffects = 1, Uses = [R0D, R1D, R2D, R3D], Defs = [CC] in
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def SIGA : SideEffectAddressS<"siga", 0xB274, null_frag>;
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// Start interpretive execution.
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let hasSideEffects = 1, Defs = [CC] in
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def SIE : SideEffectUnaryS<"sie", 0xB214, null_frag, 0>;
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//===----------------------------------------------------------------------===//
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// CPU-Measurement Facility Instructions (SA23-2260).
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//===----------------------------------------------------------------------===//
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// Load program parameter
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let hasSideEffects = 1 in
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def LPP : SideEffectUnaryS<"lpp", 0xB280, null_frag, 8>;
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// Extract coprocessor-group address.
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let hasSideEffects = 1, Defs = [CC] in
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def ECPGA : UnaryRRE<"ecpga", 0xB2ED, null_frag, GR32, GR64>;
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// Extract CPU counter.
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let hasSideEffects = 1, Defs = [CC] in
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def ECCTR : UnaryRRE<"ecctr", 0xB2E4, null_frag, GR64, GR64>;
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// Extract peripheral counter.
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let hasSideEffects = 1, Defs = [CC] in
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def EPCTR : UnaryRRE<"epctr", 0xB2E5, null_frag, GR64, GR64>;
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// Load CPU-counter-set controls.
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let hasSideEffects = 1, Defs = [CC] in
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def LCCTL : SideEffectUnaryS<"lcctl", 0xB284, null_frag, 8>;
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// Load peripheral-counter-set controls.
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let hasSideEffects = 1, Defs = [CC] in
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def LPCTL : SideEffectUnaryS<"lpctl", 0xB285, null_frag, 8>;
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// Load sampling controls.
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let hasSideEffects = 1, Defs = [CC] in
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def LSCTL : SideEffectUnaryS<"lsctl", 0xB287, null_frag, 0>;
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// Query sampling information.
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let hasSideEffects = 1 in
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def QSI : StoreInherentS<"qsi", 0xB286, null_frag, 0>;
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// Query counter information.
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let hasSideEffects = 1 in
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def QCTRI : StoreInherentS<"qctri", 0xB28E, null_frag, 0>;
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// Set CPU counter.
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let hasSideEffects = 1, Defs = [CC] in
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def SCCTR : SideEffectBinaryRRE<"scctr", 0xB2E0, GR64, GR64>;
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// Set peripheral counter.
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let hasSideEffects = 1, Defs = [CC] in
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def SPCTR : SideEffectBinaryRRE<"spctr", 0xB2E1, GR64, GR64>;
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//===----------------------------------------------------------------------===//
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// I/O Instructions (Principles of Operation, Chapter 14).
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//===----------------------------------------------------------------------===//
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// Clear subchannel.
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let hasSideEffects = 1, Uses = [R1L], Defs = [CC] in
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def CSCH : SideEffectInherentS<"csch", 0xB230, null_frag>;
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// Halt subchannel.
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let hasSideEffects = 1, Uses = [R1L], Defs = [CC] in
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def HSCH : SideEffectInherentS<"hsch", 0xB231, null_frag>;
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// Modify subchannel.
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let hasSideEffects = 1, Uses = [R1L], Defs = [CC] in
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def MSCH : SideEffectUnaryS<"msch", 0xB232, null_frag, 0>;
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// Resume subchannel.
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let hasSideEffects = 1, Uses = [R1L], Defs = [CC] in
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def RSCH : SideEffectInherentS<"rsch", 0xB238, null_frag>;
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// Start subchannel.
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let hasSideEffects = 1, Uses = [R1L], Defs = [CC] in
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def SSCH : SideEffectUnaryS<"ssch", 0xB233, null_frag, 0>;
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// Store subchannel.
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let hasSideEffects = 1, Uses = [R1L], Defs = [CC] in
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def STSCH : StoreInherentS<"stsch", 0xB234, null_frag, 0>;
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// Test subchannel.
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let hasSideEffects = 1, Uses = [R1L], Defs = [CC] in
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def TSCH : StoreInherentS<"tsch", 0xB235, null_frag, 0>;
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// Cancel subchannel.
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let hasSideEffects = 1, Uses = [R1L], Defs = [CC] in
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def XSCH : SideEffectInherentS<"xsch", 0xB276, null_frag>;
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// Reset channel path.
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let hasSideEffects = 1, Uses = [R1L], Defs = [CC] in
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def RCHP : SideEffectInherentS<"rchp", 0xB23B, null_frag>;
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// Set channel monitor.
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let hasSideEffects = 1, mayLoad = 1, Uses = [R1L, R2D] in
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def SCHM : SideEffectInherentS<"schm", 0xB23C, null_frag>;
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// Store channel path status.
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let hasSideEffects = 1 in
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def STCPS : StoreInherentS<"stcps", 0xB23A, null_frag, 0>;
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// Store channel report word.
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let hasSideEffects = 1, Defs = [CC] in
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def STCRW : StoreInherentS<"stcrw", 0xB239, null_frag, 0>;
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// Test pending interruption.
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let hasSideEffects = 1, Defs = [CC] in
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def TPI : StoreInherentS<"tpi", 0xB236, null_frag, 0>;
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// Set address limit.
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let hasSideEffects = 1, Uses = [R1L] in
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def SAL : SideEffectInherentS<"sal", 0xB237, null_frag>;
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