llvm-project/llvm/lib/Target/SystemZ
Simon Pilgrim 8c4069e842 [SystemZ] Fix -Wimplicit-fallthrough warnings. NFCI.
llvm-svn: 307376
2017-07-07 10:07:09 +00:00
..
AsmParser [SystemZ] Add all remaining instructions 2017-06-30 20:43:40 +00:00
Disassembler [SystemZ] Add all remaining instructions 2017-06-30 20:43:40 +00:00
InstPrinter [SystemZ] Fix some Include What You Use warnings; other minor fixes (NFC). 2017-02-03 23:39:06 +00:00
MCTargetDesc [SystemZ] Add all remaining instructions 2017-06-30 20:43:40 +00:00
TargetInfo
CMakeLists.txt [SystemZ] Improve use of conditional instructions 2016-11-28 13:34:08 +00:00
LLVMBuild.txt
README.txt [SystemZ] Add missing high-word facility instructions 2017-06-30 12:56:29 +00:00
SystemZ.h [SystemZ] Improve use of conditional instructions 2016-11-28 13:34:08 +00:00
SystemZ.td [SystemZ] Add all remaining instructions 2017-06-30 20:43:40 +00:00
SystemZAsmPrinter.cpp [SystemZ] Refactor branch and conditional instruction patterns 2016-11-08 18:30:50 +00:00
SystemZAsmPrinter.h
SystemZCallingConv.cpp
SystemZCallingConv.h
SystemZCallingConv.td
SystemZConstantPoolValue.cpp
SystemZConstantPoolValue.h
SystemZElimCompare.cpp [SystemZ] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-01-24 22:10:43 +00:00
SystemZExpandPseudo.cpp LivePhysRegs: Rework constructor + documentation; NFC 2017-05-26 21:51:00 +00:00
SystemZFeatures.td [SystemZ] Add all remaining instructions 2017-06-30 20:43:40 +00:00
SystemZFrameLowering.cpp [SystemZ] Fix missing emergency spill slot corner case 2017-06-26 16:50:32 +00:00
SystemZFrameLowering.h
SystemZHazardRecognizer.cpp Give some helper classes/functions internal linkage. NFC. 2016-11-19 20:44:26 +00:00
SystemZHazardRecognizer.h Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
SystemZISelDAGToDAG.cpp [SelectionDAG] Use KnownBits struct in DAG's computeKnownBits and simplifyDemandedBits 2017-04-28 05:31:46 +00:00
SystemZISelLowering.cpp [SystemZ] Fix -Wimplicit-fallthrough warnings. NFCI. 2017-07-07 10:07:09 +00:00
SystemZISelLowering.h [SystemZ] Simplify handling of 128-bit multiply/divide instruction 2017-07-05 13:17:31 +00:00
SystemZInstrBuilder.h
SystemZInstrDFP.td [SystemZ] Add decimal floating-point instructions 2017-05-30 10:15:16 +00:00
SystemZInstrFP.td [SystemZ] Add hexadecimal floating-point instructions 2017-05-30 10:13:23 +00:00
SystemZInstrFormats.td [SystemZ] Add all remaining instructions 2017-06-30 20:43:40 +00:00
SystemZInstrHFP.td [SystemZ] Add hexadecimal floating-point instructions 2017-05-30 10:13:23 +00:00
SystemZInstrInfo.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
SystemZInstrInfo.h [SystemZ] Don't drop any operands in expandZExtPseudo() 2017-03-22 06:03:32 +00:00
SystemZInstrInfo.td [SystemZ] Simplify handling of 128-bit multiply/divide instruction 2017-07-05 13:17:31 +00:00
SystemZInstrSystem.td [SystemZ] Add all remaining instructions 2017-06-30 20:43:40 +00:00
SystemZInstrVector.td [SystemZ] Mark vector immediate load instructions with useful flags. 2017-01-23 14:09:58 +00:00
SystemZLDCleanup.cpp fix trivial typos in comments; NFC 2017-07-03 06:32:59 +00:00
SystemZLongBranch.cpp [SystemZ] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-01-24 22:10:43 +00:00
SystemZMCInstLower.cpp
SystemZMCInstLower.h
SystemZMachineFunctionInfo.cpp
SystemZMachineFunctionInfo.h
SystemZMachineScheduler.cpp Fix build. 2017-06-21 23:02:57 +00:00
SystemZMachineScheduler.h Mark dump() methods as const. NFC 2017-06-21 22:19:17 +00:00
SystemZOperands.td [SystemZ] Add decimal integer instructions 2017-05-10 12:42:45 +00:00
SystemZOperators.td [SystemZ] Simplify handling of 128-bit multiply/divide instruction 2017-07-05 13:17:31 +00:00
SystemZPatterns.td
SystemZProcessors.td
SystemZRegisterInfo.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
SystemZRegisterInfo.h
SystemZRegisterInfo.td [SystemZ] Add all remaining instructions 2017-06-30 20:43:40 +00:00
SystemZSchedule.td [SystemZ] Add decimal integer instructions 2017-05-10 12:42:45 +00:00
SystemZScheduleZ13.td [SystemZ] Simplify handling of 128-bit multiply/divide instruction 2017-07-05 13:17:31 +00:00
SystemZScheduleZ196.td [SystemZ] Simplify handling of 128-bit multiply/divide instruction 2017-07-05 13:17:31 +00:00
SystemZScheduleZEC12.td [SystemZ] Simplify handling of 128-bit multiply/divide instruction 2017-07-05 13:17:31 +00:00
SystemZSelectionDAGInfo.cpp
SystemZSelectionDAGInfo.h
SystemZShortenInst.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
SystemZSubtarget.cpp [SystemZ] Add all remaining instructions 2017-06-30 20:43:40 +00:00
SystemZSubtarget.h [SystemZ] Add all remaining instructions 2017-06-30 20:43:40 +00:00
SystemZTDC.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
SystemZTargetMachine.cpp Sort the remaining #include lines in include/... and lib/.... 2017-06-06 11:49:48 +00:00
SystemZTargetMachine.h [SystemZ] Fix trap issue and enable expensive checks. 2017-06-23 14:30:46 +00:00
SystemZTargetTransformInfo.cpp [LoopUnroll] Pass SCEV to getUnrollingPreferences hook. NFCI. 2017-06-28 15:53:17 +00:00
SystemZTargetTransformInfo.h [LoopUnroll] Pass SCEV to getUnrollingPreferences hook. NFCI. 2017-06-28 15:53:17 +00:00

README.txt

//===---------------------------------------------------------------------===//
// Random notes about and ideas for the SystemZ backend.
//===---------------------------------------------------------------------===//

The initial backend is deliberately restricted to z10.  We should add support
for later architectures at some point.

--

If an inline asm ties an i32 "r" result to an i64 input, the input
will be treated as an i32, leaving the upper bits uninitialised.
For example:

define void @f4(i32 *%dst) {
  %val = call i32 asm "blah $0", "=r,0" (i64 103)
  store i32 %val, i32 *%dst
  ret void
}

from CodeGen/SystemZ/asm-09.ll will use LHI rather than LGHI.
to load 103.  This seems to be a general target-independent problem.

--

The tuning of the choice between LOAD ADDRESS (LA) and addition in
SystemZISelDAGToDAG.cpp is suspect.  It should be tweaked based on
performance measurements.

--

There is no scheduling support.

--

We don't use the BRANCH ON INDEX instructions.

--

We only use MVC, XC and CLC for constant-length block operations.
We could extend them to variable-length operations too,
using EXECUTE RELATIVE LONG.

MVCIN, MVCLE and CLCLE may be worthwhile too.

--

We don't use CUSE or the TRANSLATE family of instructions for string
operations.  The TRANSLATE ones are probably more difficult to exploit.

--

We don't take full advantage of builtins like fabsl because the calling
conventions require f128s to be returned by invisible reference.

--

ADD LOGICAL WITH SIGNED IMMEDIATE could be useful when we need to
produce a carry.  SUBTRACT LOGICAL IMMEDIATE could be useful when we
need to produce a borrow.  (Note that there are no memory forms of
ADD LOGICAL WITH CARRY and SUBTRACT LOGICAL WITH BORROW, so the high
part of 128-bit memory operations would probably need to be done
via a register.)

--

We don't use ICM, STCM, or CLM.

--

We don't use ADD (LOGICAL) HIGH, SUBTRACT (LOGICAL) HIGH,
or COMPARE (LOGICAL) HIGH yet.

--

DAGCombiner doesn't yet fold truncations of extended loads.  Functions like:

    unsigned long f (unsigned long x, unsigned short *y)
    {
      return (x << 32) | *y;
    }

therefore end up as:

        sllg    %r2, %r2, 32
        llgh    %r0, 0(%r3)
        lr      %r2, %r0
        br      %r14

but truncating the load would give:

        sllg    %r2, %r2, 32
        lh      %r2, 0(%r3)
        br      %r14

--

Functions like:

define i64 @f1(i64 %a) {
  %and = and i64 %a, 1
  ret i64 %and
}

ought to be implemented as:

        lhi     %r0, 1
        ngr     %r2, %r0
        br      %r14

but two-address optimizations reverse the order of the AND and force:

        lhi     %r0, 1
        ngr     %r0, %r2
        lgr     %r2, %r0
        br      %r14

CodeGen/SystemZ/and-04.ll has several examples of this.

--

Out-of-range displacements are usually handled by loading the full
address into a register.  In many cases it would be better to create
an anchor point instead.  E.g. for:

define void @f4a(i128 *%aptr, i64 %base) {
  %addr = add i64 %base, 524288
  %bptr = inttoptr i64 %addr to i128 *
  %a = load volatile i128 *%aptr
  %b = load i128 *%bptr
  %add = add i128 %a, %b
  store i128 %add, i128 *%aptr
  ret void
}

(from CodeGen/SystemZ/int-add-08.ll) we load %base+524288 and %base+524296
into separate registers, rather than using %base+524288 as a base for both.

--

Dynamic stack allocations round the size to 8 bytes and then allocate
that rounded amount.  It would be simpler to subtract the unrounded
size from the copy of the stack pointer and then align the result.
See CodeGen/SystemZ/alloca-01.ll for an example.

--

If needed, we can support 16-byte atomics using LPQ, STPQ and CSDG.

--

We might want to model all access registers and use them to spill
32-bit values.

--

We might want to use the 'overflow' condition of eg. AR to support
llvm.sadd.with.overflow.i32 and related instructions - the generated code
for signed overflow check is currently quite bad.  This would improve
the results of using -ftrapv.