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llvm-project/llvm/test/CodeGen
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Tom Stellard 2860a428f7 AMDGPU/GlobalISel: Mark 32-bit G_SELECT as legal 
Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D33949

llvm-svn: 304910
 		2017-06-07 13:54:51 +00:00
..
AArch64 [Improve CodeGen Testing] This patch renables MIRPrinter print fields which have value equal to its default. 2017-06-06 08:16:19 +00:00
AMDGPU AMDGPU/GlobalISel: Mark 32-bit G_SELECT as legal 2017-06-07 13:54:51 +00:00
ARM [ARM] GlobalISel: Purge G_SEQUENCE 2017-06-07 12:35:05 +00:00
AVR [AVR] Fix a big in shift operator lowering; Authored by Dr. Gergo Erdi 2017-05-31 06:27:46 +00:00
BPF [bpf] fix a bug which causes incorrect big endian reloc fixup 2017-05-05 18:05:00 +00:00
Generic CodeGen/LLVMTargetMachine: Refactor ISel pass construction; NFCI 2017-06-06 00:26:13 +00:00
Hexagon [Hexagon] Return 0 from getDotNewPredOp when .new opcode does not exist 2017-06-02 14:07:06 +00:00
Inputs
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Lanai CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
MIR llc: Add ability to parse mir from stdin 2017-06-06 20:06:57 +00:00
MSP430 [MSP430] Fix PR33050: Don't use ADD16ri to lower FrameIndex. 2017-05-24 15:08:30 +00:00
Mips [mips] do not use FastISel when -mxgot is present 2017-06-07 12:59:53 +00:00
NVPTX Revert r302938 "Add LiveRangeShrink pass to shrink live range within BB." 2017-05-18 18:50:05 +00:00
Nios2 [Nios2] Target registration 2017-05-29 09:48:30 +00:00
PowerPC [PowerPC] Eliminate integer compare instructions - vol. 5 2017-06-07 13:18:06 +00:00
SPARC Revert r302938 "Add LiveRangeShrink pass to shrink live range within BB." 2017-05-18 18:50:05 +00:00
SystemZ [SystemZ] Simplify test case. NFC 2017-06-02 23:40:58 +00:00
Thumb Move machine-cse-physreg.mir to test/CodeGen/Thumb 2017-05-24 17:20:47 +00:00
Thumb2 MIR: remove explicit "noVRegs" property. 2017-05-30 21:28:57 +00:00
WebAssembly [wasm] Fix test after r304117. 2017-05-29 16:32:52 +00:00
WinEH
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X86 [x86] avoid flipping sign bits for vector icmp by using known bits 2017-06-07 13:46:34 +00:00
XCore AsmPrinter: mark the beginning and the end of a function in verbose mode 2017-05-23 21:22:16 +00:00