forked from OSchip/llvm-project
27 lines
782 B
TableGen
27 lines
782 B
TableGen
// RUN: mlir-tblgen -gen-directive-decl -I %S/../../../llvm/include %s | FileCheck -match-full-lines %s
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include "llvm/Frontend/Directive/DirectiveBase.td"
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def TDLCV_vala : ClauseVal<"vala",1,1> {}
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def TDLCV_valb : ClauseVal<"valb",2,1> {}
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def TDLCV_valc : ClauseVal<"valc",3,0> { let isDefault = 1; }
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def TDLC_ClauseA : Clause<"clausea"> {
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let flangClass = "TdlClauseA";
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let enumClauseValue = "AKind";
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let allowedClauseValues = [
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TDLCV_vala,
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TDLCV_valb,
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TDLCV_valc
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];
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}
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// CHECK: def AKindvala : StrEnumAttrCase<"vala">;
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// CHECK: def AKindvalb : StrEnumAttrCase<"valb">;
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// CHECK: def AKind: StrEnumAttr<
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// CHECK: "ClauseAKind",
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// CHECK: "AKind Clause",
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// CHECK: [AKindvala,AKindvalb]> {
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// CHECK: let cppNamespace = "::mlir::omp";
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// CHECK: }
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