forked from OSchip/llvm-project
257 lines
6.9 KiB
LLVM
257 lines
6.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; InstCombine canonicalizes (c ? x | y : x) to (x | (c ? y : 0)) similar for
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; other binary operations using their identity value as the constant.
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; We can reverse this for and/or/xor. Allowing us to pull the binop into
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; the basic block we create when we expand select.
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define signext i32 @and_select_all_ones_i32(i1 zeroext %c, i32 signext %x, i32 %y) {
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; RV32I-LABEL: and_select_all_ones_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: beqz a0, .LBB0_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: and a2, a2, a1
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; RV32I-NEXT: .LBB0_2:
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and_select_all_ones_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: beqz a0, .LBB0_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: and a2, a2, a1
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; RV64I-NEXT: .LBB0_2:
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; RV64I-NEXT: sext.w a0, a2
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; RV64I-NEXT: ret
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%a = select i1 %c, i32 %x, i32 -1
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%b = and i32 %a, %y
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ret i32 %b
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}
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define i64 @and_select_all_ones_i64(i1 zeroext %c, i64 %x, i64 %y) {
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; RV32I-LABEL: and_select_all_ones_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: bnez a0, .LBB1_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: and a3, a3, a1
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; RV32I-NEXT: and a4, a4, a2
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; RV32I-NEXT: .LBB1_2:
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; RV32I-NEXT: mv a0, a3
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; RV32I-NEXT: mv a1, a4
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: and_select_all_ones_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: bnez a0, .LBB1_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: and a2, a2, a1
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; RV64I-NEXT: .LBB1_2:
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; RV64I-NEXT: mv a0, a2
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; RV64I-NEXT: ret
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%a = select i1 %c, i64 -1, i64 %x
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%b = and i64 %y, %a
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ret i64 %b
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}
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define signext i32 @or_select_all_zeros_i32(i1 zeroext %c, i32 signext %x, i32 signext %y) {
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; RV32I-LABEL: or_select_all_zeros_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: beqz a0, .LBB2_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: or a2, a2, a1
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; RV32I-NEXT: .LBB2_2:
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: or_select_all_zeros_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: beqz a0, .LBB2_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: or a2, a2, a1
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; RV64I-NEXT: .LBB2_2:
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; RV64I-NEXT: mv a0, a2
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; RV64I-NEXT: ret
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%a = select i1 %c, i32 %x, i32 0
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%b = or i32 %y, %a
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ret i32 %b
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}
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define i64 @or_select_all_zeros_i64(i1 zeroext %c, i64 %x, i64 %y) {
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; RV32I-LABEL: or_select_all_zeros_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: bnez a0, .LBB3_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: or a3, a3, a1
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; RV32I-NEXT: or a4, a4, a2
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; RV32I-NEXT: .LBB3_2:
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; RV32I-NEXT: mv a0, a3
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; RV32I-NEXT: mv a1, a4
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: or_select_all_zeros_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: bnez a0, .LBB3_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: or a2, a2, a1
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; RV64I-NEXT: .LBB3_2:
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; RV64I-NEXT: mv a0, a2
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; RV64I-NEXT: ret
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%a = select i1 %c, i64 0, i64 %x
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%b = or i64 %a, %y
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ret i64 %b
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}
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define signext i32 @xor_select_all_zeros_i32(i1 zeroext %c, i32 signext %x, i32 signext %y) {
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; RV32I-LABEL: xor_select_all_zeros_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: bnez a0, .LBB4_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: xor a2, a2, a1
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; RV32I-NEXT: .LBB4_2:
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: xor_select_all_zeros_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: bnez a0, .LBB4_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: xor a2, a2, a1
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; RV64I-NEXT: .LBB4_2:
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; RV64I-NEXT: mv a0, a2
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; RV64I-NEXT: ret
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%a = select i1 %c, i32 0, i32 %x
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%b = xor i32 %y, %a
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ret i32 %b
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}
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define i64 @xor_select_all_zeros_i64(i1 zeroext %c, i64 %x, i64 %y) {
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; RV32I-LABEL: xor_select_all_zeros_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: beqz a0, .LBB5_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: xor a3, a3, a1
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; RV32I-NEXT: xor a4, a4, a2
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; RV32I-NEXT: .LBB5_2:
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; RV32I-NEXT: mv a0, a3
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; RV32I-NEXT: mv a1, a4
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: xor_select_all_zeros_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: beqz a0, .LBB5_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: xor a2, a2, a1
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; RV64I-NEXT: .LBB5_2:
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; RV64I-NEXT: mv a0, a2
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; RV64I-NEXT: ret
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%a = select i1 %c, i64 %x, i64 0
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%b = xor i64 %a, %y
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ret i64 %b
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}
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define signext i32 @add_select_all_zeros_i32(i1 zeroext %c, i32 signext %x, i32 signext %y) {
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; RV32I-LABEL: add_select_all_zeros_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: bnez a0, .LBB6_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: add a2, a2, a1
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; RV32I-NEXT: .LBB6_2:
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add_select_all_zeros_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: bnez a0, .LBB6_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: addw a2, a2, a1
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; RV64I-NEXT: .LBB6_2:
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; RV64I-NEXT: mv a0, a2
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; RV64I-NEXT: ret
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%a = select i1 %c, i32 0, i32 %x
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%b = add i32 %y, %a
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ret i32 %b
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}
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define i64 @add_select_all_zeros_i64(i1 zeroext %c, i64 %x, i64 %y) {
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; RV32I-LABEL: add_select_all_zeros_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: beqz a0, .LBB7_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: add a0, a4, a2
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; RV32I-NEXT: add a1, a3, a1
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; RV32I-NEXT: sltu a2, a1, a3
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; RV32I-NEXT: add a4, a0, a2
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; RV32I-NEXT: mv a3, a1
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; RV32I-NEXT: .LBB7_2:
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; RV32I-NEXT: mv a0, a3
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; RV32I-NEXT: mv a1, a4
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: add_select_all_zeros_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: beqz a0, .LBB7_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: add a2, a2, a1
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; RV64I-NEXT: .LBB7_2:
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; RV64I-NEXT: mv a0, a2
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; RV64I-NEXT: ret
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%a = select i1 %c, i64 %x, i64 0
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%b = add i64 %a, %y
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ret i64 %b
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}
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define signext i32 @sub_select_all_zeros_i32(i1 zeroext %c, i32 signext %x, i32 signext %y) {
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; RV32I-LABEL: sub_select_all_zeros_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: bnez a0, .LBB8_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: sub a2, a2, a1
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; RV32I-NEXT: .LBB8_2:
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: sub_select_all_zeros_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: bnez a0, .LBB8_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: subw a2, a2, a1
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; RV64I-NEXT: .LBB8_2:
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; RV64I-NEXT: mv a0, a2
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; RV64I-NEXT: ret
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%a = select i1 %c, i32 0, i32 %x
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%b = sub i32 %y, %a
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ret i32 %b
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}
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define i64 @sub_select_all_zeros_i64(i1 zeroext %c, i64 %x, i64 %y) {
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; RV32I-LABEL: sub_select_all_zeros_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: beqz a0, .LBB9_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: sltu a0, a3, a1
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; RV32I-NEXT: sub a2, a4, a2
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; RV32I-NEXT: sub a4, a2, a0
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; RV32I-NEXT: sub a3, a3, a1
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; RV32I-NEXT: .LBB9_2:
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; RV32I-NEXT: mv a0, a3
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; RV32I-NEXT: mv a1, a4
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: sub_select_all_zeros_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: beqz a0, .LBB9_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: sub a2, a2, a1
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; RV64I-NEXT: .LBB9_2:
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; RV64I-NEXT: mv a0, a2
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; RV64I-NEXT: ret
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%a = select i1 %c, i64 %x, i64 0
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%b = sub i64 %y, %a
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ret i64 %b
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}
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