forked from OSchip/llvm-project
51 lines
1.6 KiB
YAML
51 lines
1.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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# RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-v -o - %s \
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# RUN: -start-before=prologepilog | FileCheck %s
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#
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# This test checks that we are assigning the right stack slot to GPRs and to
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# vector registers (VRs). If this test changes, make sure there is no overlap
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# between slots for GPRs and VRs.
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--- |
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define void @foo() #0 {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi sp, sp, -32
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; CHECK-NEXT: sw s9, 28(sp) # 4-byte Folded Spill
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: slli a1, a1, 1
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; CHECK-NEXT: sub sp, sp, a1
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; CHECK-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
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; CHECK-NEXT: addi a0, sp, 16
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; CHECK-NEXT: vs2r.v v30, (a0) # Unknown-size Folded Spill
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: slli a0, a0, 1
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; CHECK-NEXT: add sp, sp, a0
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; CHECK-NEXT: lw s9, 28(sp) # 4-byte Folded Reload
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; CHECK-NEXT: addi sp, sp, 32
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; CHECK-NEXT: ret
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entry:
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ret void
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}
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attributes #0 = { nounwind }
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...
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---
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name: foo
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alignment: 2
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frameInfo:
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maxAlignment: 8
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stack:
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- { id: 0, type: spill-slot, size: 4, alignment: 4 }
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- { id: 1, type: spill-slot, size: 16, alignment: 8, stack-id: scalable-vector }
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $x10, $v30m2
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$x25 = COPY $x10
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SW renamable $x25, %stack.0, 0 :: (store (s32) into %stack.0)
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PseudoVSPILL_M2 renamable $v30m2, %stack.1 :: (store unknown-size into %stack.1, align 8)
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PseudoRET
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...
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