forked from OSchip/llvm-project
1705 lines
44 KiB
LLVM
1705 lines
44 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
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; RUN: < %s | FileCheck %s
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declare void @llvm.riscv.vsse.nxv1i64(
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<vscale x 1 x i64>,
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<vscale x 1 x i64>*,
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i64,
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i64);
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define void @intrinsic_vsse_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, i64 %2, i64 %3) nounwind {
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; CHECK-LABEL: intrinsic_vsse_v_nxv1i64_nxv1i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
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; CHECK-NEXT: vsse64.v v8, (a0), a1
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; CHECK-NEXT: ret
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entry:
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call void @llvm.riscv.vsse.nxv1i64(
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<vscale x 1 x i64> %0,
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<vscale x 1 x i64>* %1,
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i64 %2,
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i64 %3)
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ret void
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}
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declare void @llvm.riscv.vsse.mask.nxv1i64(
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<vscale x 1 x i64>,
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<vscale x 1 x i64>*,
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i64,
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<vscale x 1 x i1>,
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i64);
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define void @intrinsic_vsse_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
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; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1i64_nxv1i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
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; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t
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; CHECK-NEXT: ret
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entry:
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call void @llvm.riscv.vsse.mask.nxv1i64(
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<vscale x 1 x i64> %0,
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<vscale x 1 x i64>* %1,
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i64 %2,
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<vscale x 1 x i1> %3,
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i64 %4)
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ret void
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}
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declare void @llvm.riscv.vsse.nxv2i64(
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<vscale x 2 x i64>,
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<vscale x 2 x i64>*,
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i64,
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i64);
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define void @intrinsic_vsse_v_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64>* %1, i64 %2, i64 %3) nounwind {
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; CHECK-LABEL: intrinsic_vsse_v_nxv2i64_nxv2i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
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; CHECK-NEXT: vsse64.v v8, (a0), a1
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; CHECK-NEXT: ret
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entry:
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call void @llvm.riscv.vsse.nxv2i64(
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<vscale x 2 x i64> %0,
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<vscale x 2 x i64>* %1,
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i64 %2,
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i64 %3)
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ret void
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}
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declare void @llvm.riscv.vsse.mask.nxv2i64(
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<vscale x 2 x i64>,
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<vscale x 2 x i64>*,
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i64,
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<vscale x 2 x i1>,
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i64);
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define void @intrinsic_vsse_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64>* %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
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; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2i64_nxv2i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
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; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t
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; CHECK-NEXT: ret
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entry:
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call void @llvm.riscv.vsse.mask.nxv2i64(
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<vscale x 2 x i64> %0,
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<vscale x 2 x i64>* %1,
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i64 %2,
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<vscale x 2 x i1> %3,
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i64 %4)
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ret void
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}
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declare void @llvm.riscv.vsse.nxv4i64(
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<vscale x 4 x i64>,
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<vscale x 4 x i64>*,
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i64,
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i64);
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define void @intrinsic_vsse_v_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64>* %1, i64 %2, i64 %3) nounwind {
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; CHECK-LABEL: intrinsic_vsse_v_nxv4i64_nxv4i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
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; CHECK-NEXT: vsse64.v v8, (a0), a1
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; CHECK-NEXT: ret
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entry:
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call void @llvm.riscv.vsse.nxv4i64(
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<vscale x 4 x i64> %0,
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<vscale x 4 x i64>* %1,
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i64 %2,
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i64 %3)
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ret void
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}
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declare void @llvm.riscv.vsse.mask.nxv4i64(
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<vscale x 4 x i64>,
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<vscale x 4 x i64>*,
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i64,
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<vscale x 4 x i1>,
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i64);
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define void @intrinsic_vsse_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64>* %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
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; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4i64_nxv4i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
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; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t
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; CHECK-NEXT: ret
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entry:
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call void @llvm.riscv.vsse.mask.nxv4i64(
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<vscale x 4 x i64> %0,
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<vscale x 4 x i64>* %1,
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i64 %2,
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<vscale x 4 x i1> %3,
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i64 %4)
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ret void
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}
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declare void @llvm.riscv.vsse.nxv8i64(
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<vscale x 8 x i64>,
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<vscale x 8 x i64>*,
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i64,
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i64);
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define void @intrinsic_vsse_v_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64>* %1, i64 %2, i64 %3) nounwind {
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; CHECK-LABEL: intrinsic_vsse_v_nxv8i64_nxv8i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
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; CHECK-NEXT: vsse64.v v8, (a0), a1
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; CHECK-NEXT: ret
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entry:
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call void @llvm.riscv.vsse.nxv8i64(
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<vscale x 8 x i64> %0,
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<vscale x 8 x i64>* %1,
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i64 %2,
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i64 %3)
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ret void
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}
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declare void @llvm.riscv.vsse.mask.nxv8i64(
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<vscale x 8 x i64>,
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<vscale x 8 x i64>*,
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i64,
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<vscale x 8 x i1>,
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i64);
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define void @intrinsic_vsse_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64>* %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
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; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8i64_nxv8i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
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; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t
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; CHECK-NEXT: ret
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entry:
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call void @llvm.riscv.vsse.mask.nxv8i64(
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<vscale x 8 x i64> %0,
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<vscale x 8 x i64>* %1,
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i64 %2,
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<vscale x 8 x i1> %3,
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i64 %4)
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ret void
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}
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declare void @llvm.riscv.vsse.nxv1f64(
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<vscale x 1 x double>,
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<vscale x 1 x double>*,
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i64,
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i64);
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define void @intrinsic_vsse_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, i64 %2, i64 %3) nounwind {
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; CHECK-LABEL: intrinsic_vsse_v_nxv1f64_nxv1f64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
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; CHECK-NEXT: vsse64.v v8, (a0), a1
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; CHECK-NEXT: ret
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entry:
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call void @llvm.riscv.vsse.nxv1f64(
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<vscale x 1 x double> %0,
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<vscale x 1 x double>* %1,
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i64 %2,
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i64 %3)
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ret void
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}
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declare void @llvm.riscv.vsse.mask.nxv1f64(
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<vscale x 1 x double>,
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<vscale x 1 x double>*,
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i64,
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<vscale x 1 x i1>,
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i64);
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define void @intrinsic_vsse_mask_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
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; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1f64_nxv1f64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
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; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t
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; CHECK-NEXT: ret
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entry:
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call void @llvm.riscv.vsse.mask.nxv1f64(
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<vscale x 1 x double> %0,
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<vscale x 1 x double>* %1,
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i64 %2,
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<vscale x 1 x i1> %3,
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i64 %4)
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ret void
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}
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declare void @llvm.riscv.vsse.nxv2f64(
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<vscale x 2 x double>,
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<vscale x 2 x double>*,
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i64,
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i64);
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define void @intrinsic_vsse_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double>* %1, i64 %2, i64 %3) nounwind {
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; CHECK-LABEL: intrinsic_vsse_v_nxv2f64_nxv2f64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
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; CHECK-NEXT: vsse64.v v8, (a0), a1
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; CHECK-NEXT: ret
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entry:
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call void @llvm.riscv.vsse.nxv2f64(
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<vscale x 2 x double> %0,
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<vscale x 2 x double>* %1,
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i64 %2,
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i64 %3)
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ret void
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}
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declare void @llvm.riscv.vsse.mask.nxv2f64(
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<vscale x 2 x double>,
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<vscale x 2 x double>*,
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i64,
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<vscale x 2 x i1>,
|
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i64);
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define void @intrinsic_vsse_mask_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double>* %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
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; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2f64_nxv2f64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
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; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t
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; CHECK-NEXT: ret
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entry:
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call void @llvm.riscv.vsse.mask.nxv2f64(
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<vscale x 2 x double> %0,
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<vscale x 2 x double>* %1,
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i64 %2,
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<vscale x 2 x i1> %3,
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i64 %4)
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ret void
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}
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declare void @llvm.riscv.vsse.nxv4f64(
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<vscale x 4 x double>,
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<vscale x 4 x double>*,
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i64,
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i64);
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define void @intrinsic_vsse_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double>* %1, i64 %2, i64 %3) nounwind {
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; CHECK-LABEL: intrinsic_vsse_v_nxv4f64_nxv4f64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
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; CHECK-NEXT: vsse64.v v8, (a0), a1
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; CHECK-NEXT: ret
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entry:
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call void @llvm.riscv.vsse.nxv4f64(
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<vscale x 4 x double> %0,
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<vscale x 4 x double>* %1,
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i64 %2,
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i64 %3)
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ret void
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}
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declare void @llvm.riscv.vsse.mask.nxv4f64(
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<vscale x 4 x double>,
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<vscale x 4 x double>*,
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i64,
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<vscale x 4 x i1>,
|
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i64);
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define void @intrinsic_vsse_mask_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double>* %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
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; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4f64_nxv4f64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
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; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t
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; CHECK-NEXT: ret
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entry:
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call void @llvm.riscv.vsse.mask.nxv4f64(
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<vscale x 4 x double> %0,
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<vscale x 4 x double>* %1,
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i64 %2,
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<vscale x 4 x i1> %3,
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i64 %4)
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ret void
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}
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declare void @llvm.riscv.vsse.nxv8f64(
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<vscale x 8 x double>,
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<vscale x 8 x double>*,
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i64,
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i64);
|
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|
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define void @intrinsic_vsse_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double>* %1, i64 %2, i64 %3) nounwind {
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; CHECK-LABEL: intrinsic_vsse_v_nxv8f64_nxv8f64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
|
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; CHECK-NEXT: vsse64.v v8, (a0), a1
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; CHECK-NEXT: ret
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entry:
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call void @llvm.riscv.vsse.nxv8f64(
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<vscale x 8 x double> %0,
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<vscale x 8 x double>* %1,
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i64 %2,
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i64 %3)
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ret void
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}
|
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|
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declare void @llvm.riscv.vsse.mask.nxv8f64(
|
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<vscale x 8 x double>,
|
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<vscale x 8 x double>*,
|
|
i64,
|
|
<vscale x 8 x i1>,
|
|
i64);
|
|
|
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define void @intrinsic_vsse_mask_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double>* %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
|
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; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8f64_nxv8f64:
|
|
; CHECK: # %bb.0: # %entry
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|
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
|
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; CHECK-NEXT: vsse64.v v8, (a0), a1, v0.t
|
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; CHECK-NEXT: ret
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|
entry:
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call void @llvm.riscv.vsse.mask.nxv8f64(
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<vscale x 8 x double> %0,
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<vscale x 8 x double>* %1,
|
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i64 %2,
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<vscale x 8 x i1> %3,
|
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i64 %4)
|
|
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ret void
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}
|
|
|
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declare void @llvm.riscv.vsse.nxv1i32(
|
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<vscale x 1 x i32>,
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<vscale x 1 x i32>*,
|
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i64,
|
|
i64);
|
|
|
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define void @intrinsic_vsse_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv1i32_nxv1i32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
|
|
; CHECK-NEXT: vsse32.v v8, (a0), a1
|
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; CHECK-NEXT: ret
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entry:
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call void @llvm.riscv.vsse.nxv1i32(
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<vscale x 1 x i32> %0,
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<vscale x 1 x i32>* %1,
|
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i64 %2,
|
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i64 %3)
|
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|
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ret void
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|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv1i32(
|
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<vscale x 1 x i32>,
|
|
<vscale x 1 x i32>*,
|
|
i64,
|
|
<vscale x 1 x i1>,
|
|
i64);
|
|
|
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define void @intrinsic_vsse_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1i32_nxv1i32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
|
|
; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv1i32(
|
|
<vscale x 1 x i32> %0,
|
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<vscale x 1 x i32>* %1,
|
|
i64 %2,
|
|
<vscale x 1 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv2i32(
|
|
<vscale x 2 x i32>,
|
|
<vscale x 2 x i32>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv2i32_nxv2i32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
|
|
; CHECK-NEXT: vsse32.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv2i32(
|
|
<vscale x 2 x i32> %0,
|
|
<vscale x 2 x i32>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv2i32(
|
|
<vscale x 2 x i32>,
|
|
<vscale x 2 x i32>*,
|
|
i64,
|
|
<vscale x 2 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2i32_nxv2i32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
|
|
; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv2i32(
|
|
<vscale x 2 x i32> %0,
|
|
<vscale x 2 x i32>* %1,
|
|
i64 %2,
|
|
<vscale x 2 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv4i32(
|
|
<vscale x 4 x i32>,
|
|
<vscale x 4 x i32>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv4i32_nxv4i32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
|
|
; CHECK-NEXT: vsse32.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv4i32(
|
|
<vscale x 4 x i32> %0,
|
|
<vscale x 4 x i32>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv4i32(
|
|
<vscale x 4 x i32>,
|
|
<vscale x 4 x i32>*,
|
|
i64,
|
|
<vscale x 4 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4i32_nxv4i32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
|
|
; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv4i32(
|
|
<vscale x 4 x i32> %0,
|
|
<vscale x 4 x i32>* %1,
|
|
i64 %2,
|
|
<vscale x 4 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv8i32(
|
|
<vscale x 8 x i32>,
|
|
<vscale x 8 x i32>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv8i32_nxv8i32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
|
|
; CHECK-NEXT: vsse32.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv8i32(
|
|
<vscale x 8 x i32> %0,
|
|
<vscale x 8 x i32>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv8i32(
|
|
<vscale x 8 x i32>,
|
|
<vscale x 8 x i32>*,
|
|
i64,
|
|
<vscale x 8 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8i32_nxv8i32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
|
|
; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv8i32(
|
|
<vscale x 8 x i32> %0,
|
|
<vscale x 8 x i32>* %1,
|
|
i64 %2,
|
|
<vscale x 8 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv16i32(
|
|
<vscale x 16 x i32>,
|
|
<vscale x 16 x i32>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv16i32_nxv16i32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
|
|
; CHECK-NEXT: vsse32.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv16i32(
|
|
<vscale x 16 x i32> %0,
|
|
<vscale x 16 x i32>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv16i32(
|
|
<vscale x 16 x i32>,
|
|
<vscale x 16 x i32>*,
|
|
i64,
|
|
<vscale x 16 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16i32_nxv16i32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
|
|
; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv16i32(
|
|
<vscale x 16 x i32> %0,
|
|
<vscale x 16 x i32>* %1,
|
|
i64 %2,
|
|
<vscale x 16 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv1f32(
|
|
<vscale x 1 x float>,
|
|
<vscale x 1 x float>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv1f32_nxv1f32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
|
|
; CHECK-NEXT: vsse32.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv1f32(
|
|
<vscale x 1 x float> %0,
|
|
<vscale x 1 x float>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv1f32(
|
|
<vscale x 1 x float>,
|
|
<vscale x 1 x float>*,
|
|
i64,
|
|
<vscale x 1 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1f32_nxv1f32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e32, mf2, ta, mu
|
|
; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv1f32(
|
|
<vscale x 1 x float> %0,
|
|
<vscale x 1 x float>* %1,
|
|
i64 %2,
|
|
<vscale x 1 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv2f32(
|
|
<vscale x 2 x float>,
|
|
<vscale x 2 x float>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv2f32_nxv2f32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
|
|
; CHECK-NEXT: vsse32.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv2f32(
|
|
<vscale x 2 x float> %0,
|
|
<vscale x 2 x float>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv2f32(
|
|
<vscale x 2 x float>,
|
|
<vscale x 2 x float>*,
|
|
i64,
|
|
<vscale x 2 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2f32_nxv2f32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, mu
|
|
; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv2f32(
|
|
<vscale x 2 x float> %0,
|
|
<vscale x 2 x float>* %1,
|
|
i64 %2,
|
|
<vscale x 2 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv4f32(
|
|
<vscale x 4 x float>,
|
|
<vscale x 4 x float>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv4f32_nxv4f32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
|
|
; CHECK-NEXT: vsse32.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv4f32(
|
|
<vscale x 4 x float> %0,
|
|
<vscale x 4 x float>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv4f32(
|
|
<vscale x 4 x float>,
|
|
<vscale x 4 x float>*,
|
|
i64,
|
|
<vscale x 4 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4f32_nxv4f32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e32, m2, ta, mu
|
|
; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv4f32(
|
|
<vscale x 4 x float> %0,
|
|
<vscale x 4 x float>* %1,
|
|
i64 %2,
|
|
<vscale x 4 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv8f32(
|
|
<vscale x 8 x float>,
|
|
<vscale x 8 x float>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv8f32_nxv8f32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
|
|
; CHECK-NEXT: vsse32.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv8f32(
|
|
<vscale x 8 x float> %0,
|
|
<vscale x 8 x float>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv8f32(
|
|
<vscale x 8 x float>,
|
|
<vscale x 8 x float>*,
|
|
i64,
|
|
<vscale x 8 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8f32_nxv8f32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, mu
|
|
; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv8f32(
|
|
<vscale x 8 x float> %0,
|
|
<vscale x 8 x float>* %1,
|
|
i64 %2,
|
|
<vscale x 8 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv16f32(
|
|
<vscale x 16 x float>,
|
|
<vscale x 16 x float>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv16f32_nxv16f32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
|
|
; CHECK-NEXT: vsse32.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv16f32(
|
|
<vscale x 16 x float> %0,
|
|
<vscale x 16 x float>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv16f32(
|
|
<vscale x 16 x float>,
|
|
<vscale x 16 x float>*,
|
|
i64,
|
|
<vscale x 16 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16f32_nxv16f32:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
|
|
; CHECK-NEXT: vsse32.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv16f32(
|
|
<vscale x 16 x float> %0,
|
|
<vscale x 16 x float>* %1,
|
|
i64 %2,
|
|
<vscale x 16 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv1i16(
|
|
<vscale x 1 x i16>,
|
|
<vscale x 1 x i16>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv1i16_nxv1i16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
|
|
; CHECK-NEXT: vsse16.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv1i16(
|
|
<vscale x 1 x i16> %0,
|
|
<vscale x 1 x i16>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv1i16(
|
|
<vscale x 1 x i16>,
|
|
<vscale x 1 x i16>*,
|
|
i64,
|
|
<vscale x 1 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1i16_nxv1i16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
|
|
; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv1i16(
|
|
<vscale x 1 x i16> %0,
|
|
<vscale x 1 x i16>* %1,
|
|
i64 %2,
|
|
<vscale x 1 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv2i16(
|
|
<vscale x 2 x i16>,
|
|
<vscale x 2 x i16>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv2i16_nxv2i16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
|
|
; CHECK-NEXT: vsse16.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv2i16(
|
|
<vscale x 2 x i16> %0,
|
|
<vscale x 2 x i16>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv2i16(
|
|
<vscale x 2 x i16>,
|
|
<vscale x 2 x i16>*,
|
|
i64,
|
|
<vscale x 2 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2i16_nxv2i16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
|
|
; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv2i16(
|
|
<vscale x 2 x i16> %0,
|
|
<vscale x 2 x i16>* %1,
|
|
i64 %2,
|
|
<vscale x 2 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv4i16(
|
|
<vscale x 4 x i16>,
|
|
<vscale x 4 x i16>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv4i16_nxv4i16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
|
|
; CHECK-NEXT: vsse16.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv4i16(
|
|
<vscale x 4 x i16> %0,
|
|
<vscale x 4 x i16>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv4i16(
|
|
<vscale x 4 x i16>,
|
|
<vscale x 4 x i16>*,
|
|
i64,
|
|
<vscale x 4 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4i16_nxv4i16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
|
|
; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv4i16(
|
|
<vscale x 4 x i16> %0,
|
|
<vscale x 4 x i16>* %1,
|
|
i64 %2,
|
|
<vscale x 4 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv8i16(
|
|
<vscale x 8 x i16>,
|
|
<vscale x 8 x i16>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv8i16_nxv8i16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
|
|
; CHECK-NEXT: vsse16.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv8i16(
|
|
<vscale x 8 x i16> %0,
|
|
<vscale x 8 x i16>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv8i16(
|
|
<vscale x 8 x i16>,
|
|
<vscale x 8 x i16>*,
|
|
i64,
|
|
<vscale x 8 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8i16_nxv8i16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
|
|
; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv8i16(
|
|
<vscale x 8 x i16> %0,
|
|
<vscale x 8 x i16>* %1,
|
|
i64 %2,
|
|
<vscale x 8 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv16i16(
|
|
<vscale x 16 x i16>,
|
|
<vscale x 16 x i16>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv16i16_nxv16i16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
|
|
; CHECK-NEXT: vsse16.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv16i16(
|
|
<vscale x 16 x i16> %0,
|
|
<vscale x 16 x i16>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv16i16(
|
|
<vscale x 16 x i16>,
|
|
<vscale x 16 x i16>*,
|
|
i64,
|
|
<vscale x 16 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16i16_nxv16i16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
|
|
; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv16i16(
|
|
<vscale x 16 x i16> %0,
|
|
<vscale x 16 x i16>* %1,
|
|
i64 %2,
|
|
<vscale x 16 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv32i16(
|
|
<vscale x 32 x i16>,
|
|
<vscale x 32 x i16>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv32i16_nxv32i16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
|
|
; CHECK-NEXT: vsse16.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv32i16(
|
|
<vscale x 32 x i16> %0,
|
|
<vscale x 32 x i16>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv32i16(
|
|
<vscale x 32 x i16>,
|
|
<vscale x 32 x i16>*,
|
|
i64,
|
|
<vscale x 32 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, i64 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv32i16_nxv32i16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
|
|
; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv32i16(
|
|
<vscale x 32 x i16> %0,
|
|
<vscale x 32 x i16>* %1,
|
|
i64 %2,
|
|
<vscale x 32 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv1f16(
|
|
<vscale x 1 x half>,
|
|
<vscale x 1 x half>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv1f16_nxv1f16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
|
|
; CHECK-NEXT: vsse16.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv1f16(
|
|
<vscale x 1 x half> %0,
|
|
<vscale x 1 x half>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv1f16(
|
|
<vscale x 1 x half>,
|
|
<vscale x 1 x half>*,
|
|
i64,
|
|
<vscale x 1 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1f16_nxv1f16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e16, mf4, ta, mu
|
|
; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv1f16(
|
|
<vscale x 1 x half> %0,
|
|
<vscale x 1 x half>* %1,
|
|
i64 %2,
|
|
<vscale x 1 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv2f16(
|
|
<vscale x 2 x half>,
|
|
<vscale x 2 x half>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv2f16_nxv2f16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
|
|
; CHECK-NEXT: vsse16.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv2f16(
|
|
<vscale x 2 x half> %0,
|
|
<vscale x 2 x half>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv2f16(
|
|
<vscale x 2 x half>,
|
|
<vscale x 2 x half>*,
|
|
i64,
|
|
<vscale x 2 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2f16_nxv2f16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e16, mf2, ta, mu
|
|
; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv2f16(
|
|
<vscale x 2 x half> %0,
|
|
<vscale x 2 x half>* %1,
|
|
i64 %2,
|
|
<vscale x 2 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv4f16(
|
|
<vscale x 4 x half>,
|
|
<vscale x 4 x half>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv4f16_nxv4f16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
|
|
; CHECK-NEXT: vsse16.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv4f16(
|
|
<vscale x 4 x half> %0,
|
|
<vscale x 4 x half>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv4f16(
|
|
<vscale x 4 x half>,
|
|
<vscale x 4 x half>*,
|
|
i64,
|
|
<vscale x 4 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4f16_nxv4f16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e16, m1, ta, mu
|
|
; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv4f16(
|
|
<vscale x 4 x half> %0,
|
|
<vscale x 4 x half>* %1,
|
|
i64 %2,
|
|
<vscale x 4 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv8f16(
|
|
<vscale x 8 x half>,
|
|
<vscale x 8 x half>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv8f16_nxv8f16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
|
|
; CHECK-NEXT: vsse16.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv8f16(
|
|
<vscale x 8 x half> %0,
|
|
<vscale x 8 x half>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv8f16(
|
|
<vscale x 8 x half>,
|
|
<vscale x 8 x half>*,
|
|
i64,
|
|
<vscale x 8 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8f16_nxv8f16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e16, m2, ta, mu
|
|
; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv8f16(
|
|
<vscale x 8 x half> %0,
|
|
<vscale x 8 x half>* %1,
|
|
i64 %2,
|
|
<vscale x 8 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv16f16(
|
|
<vscale x 16 x half>,
|
|
<vscale x 16 x half>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv16f16_nxv16f16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
|
|
; CHECK-NEXT: vsse16.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv16f16(
|
|
<vscale x 16 x half> %0,
|
|
<vscale x 16 x half>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv16f16(
|
|
<vscale x 16 x half>,
|
|
<vscale x 16 x half>*,
|
|
i64,
|
|
<vscale x 16 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16f16_nxv16f16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
|
|
; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv16f16(
|
|
<vscale x 16 x half> %0,
|
|
<vscale x 16 x half>* %1,
|
|
i64 %2,
|
|
<vscale x 16 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv32f16(
|
|
<vscale x 32 x half>,
|
|
<vscale x 32 x half>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv32f16_nxv32f16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
|
|
; CHECK-NEXT: vsse16.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv32f16(
|
|
<vscale x 32 x half> %0,
|
|
<vscale x 32 x half>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv32f16(
|
|
<vscale x 32 x half>,
|
|
<vscale x 32 x half>*,
|
|
i64,
|
|
<vscale x 32 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half>* %1, i64 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv32f16_nxv32f16:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
|
|
; CHECK-NEXT: vsse16.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv32f16(
|
|
<vscale x 32 x half> %0,
|
|
<vscale x 32 x half>* %1,
|
|
i64 %2,
|
|
<vscale x 32 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv1i8(
|
|
<vscale x 1 x i8>,
|
|
<vscale x 1 x i8>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv1i8_nxv1i8:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
|
|
; CHECK-NEXT: vsse8.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv1i8(
|
|
<vscale x 1 x i8> %0,
|
|
<vscale x 1 x i8>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv1i8(
|
|
<vscale x 1 x i8>,
|
|
<vscale x 1 x i8>*,
|
|
i64,
|
|
<vscale x 1 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv1i8_nxv1i8:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e8, mf8, ta, mu
|
|
; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv1i8(
|
|
<vscale x 1 x i8> %0,
|
|
<vscale x 1 x i8>* %1,
|
|
i64 %2,
|
|
<vscale x 1 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv2i8(
|
|
<vscale x 2 x i8>,
|
|
<vscale x 2 x i8>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv2i8_nxv2i8:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
|
|
; CHECK-NEXT: vsse8.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv2i8(
|
|
<vscale x 2 x i8> %0,
|
|
<vscale x 2 x i8>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv2i8(
|
|
<vscale x 2 x i8>,
|
|
<vscale x 2 x i8>*,
|
|
i64,
|
|
<vscale x 2 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv2i8_nxv2i8:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e8, mf4, ta, mu
|
|
; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv2i8(
|
|
<vscale x 2 x i8> %0,
|
|
<vscale x 2 x i8>* %1,
|
|
i64 %2,
|
|
<vscale x 2 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv4i8(
|
|
<vscale x 4 x i8>,
|
|
<vscale x 4 x i8>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv4i8_nxv4i8:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
|
|
; CHECK-NEXT: vsse8.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv4i8(
|
|
<vscale x 4 x i8> %0,
|
|
<vscale x 4 x i8>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv4i8(
|
|
<vscale x 4 x i8>,
|
|
<vscale x 4 x i8>*,
|
|
i64,
|
|
<vscale x 4 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv4i8_nxv4i8:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e8, mf2, ta, mu
|
|
; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv4i8(
|
|
<vscale x 4 x i8> %0,
|
|
<vscale x 4 x i8>* %1,
|
|
i64 %2,
|
|
<vscale x 4 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv8i8(
|
|
<vscale x 8 x i8>,
|
|
<vscale x 8 x i8>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv8i8_nxv8i8:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
|
|
; CHECK-NEXT: vsse8.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv8i8(
|
|
<vscale x 8 x i8> %0,
|
|
<vscale x 8 x i8>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv8i8(
|
|
<vscale x 8 x i8>,
|
|
<vscale x 8 x i8>*,
|
|
i64,
|
|
<vscale x 8 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv8i8_nxv8i8:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, mu
|
|
; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv8i8(
|
|
<vscale x 8 x i8> %0,
|
|
<vscale x 8 x i8>* %1,
|
|
i64 %2,
|
|
<vscale x 8 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv16i8(
|
|
<vscale x 16 x i8>,
|
|
<vscale x 16 x i8>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv16i8_nxv16i8:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
|
|
; CHECK-NEXT: vsse8.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv16i8(
|
|
<vscale x 16 x i8> %0,
|
|
<vscale x 16 x i8>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv16i8(
|
|
<vscale x 16 x i8>,
|
|
<vscale x 16 x i8>*,
|
|
i64,
|
|
<vscale x 16 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, i64 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv16i8_nxv16i8:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
|
|
; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv16i8(
|
|
<vscale x 16 x i8> %0,
|
|
<vscale x 16 x i8>* %1,
|
|
i64 %2,
|
|
<vscale x 16 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv32i8(
|
|
<vscale x 32 x i8>,
|
|
<vscale x 32 x i8>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv32i8_nxv32i8:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
|
|
; CHECK-NEXT: vsse8.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv32i8(
|
|
<vscale x 32 x i8> %0,
|
|
<vscale x 32 x i8>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv32i8(
|
|
<vscale x 32 x i8>,
|
|
<vscale x 32 x i8>*,
|
|
i64,
|
|
<vscale x 32 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, i64 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_mask_v_nxv32i8_nxv32i8:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
|
|
; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.mask.nxv32i8(
|
|
<vscale x 32 x i8> %0,
|
|
<vscale x 32 x i8>* %1,
|
|
i64 %2,
|
|
<vscale x 32 x i1> %3,
|
|
i64 %4)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.nxv64i8(
|
|
<vscale x 64 x i8>,
|
|
<vscale x 64 x i8>*,
|
|
i64,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_v_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8>* %1, i64 %2, i64 %3) nounwind {
|
|
; CHECK-LABEL: intrinsic_vsse_v_nxv64i8_nxv64i8:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, mu
|
|
; CHECK-NEXT: vsse8.v v8, (a0), a1
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
call void @llvm.riscv.vsse.nxv64i8(
|
|
<vscale x 64 x i8> %0,
|
|
<vscale x 64 x i8>* %1,
|
|
i64 %2,
|
|
i64 %3)
|
|
|
|
ret void
|
|
}
|
|
|
|
declare void @llvm.riscv.vsse.mask.nxv64i8(
|
|
<vscale x 64 x i8>,
|
|
<vscale x 64 x i8>*,
|
|
i64,
|
|
<vscale x 64 x i1>,
|
|
i64);
|
|
|
|
define void @intrinsic_vsse_mask_v_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8>* %1, i64 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
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; CHECK-LABEL: intrinsic_vsse_mask_v_nxv64i8_nxv64i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, mu
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; CHECK-NEXT: vsse8.v v8, (a0), a1, v0.t
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; CHECK-NEXT: ret
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entry:
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call void @llvm.riscv.vsse.mask.nxv64i8(
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<vscale x 64 x i8> %0,
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<vscale x 64 x i8>* %1,
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i64 %2,
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<vscale x 64 x i1> %3,
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i64 %4)
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ret void
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}
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