forked from OSchip/llvm-project
108 lines
4.0 KiB
LLVM
108 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+f,+d,+experimental-zfh,+experimental-v -target-abi ilp32d -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=RV32V
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; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+experimental-zfh,+experimental-v -target-abi lp64d -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefix=RV64V
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define <vscale x 8 x half> @vsplat_nxv8f16(half %f) {
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; RV32V-LABEL: vsplat_nxv8f16:
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; RV32V: # %bb.0:
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; RV32V-NEXT: vsetvli a0, zero, e16, m2, ta, mu
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; RV32V-NEXT: vfmv.v.f v8, fa0
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; RV32V-NEXT: ret
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;
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; RV64V-LABEL: vsplat_nxv8f16:
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; RV64V: # %bb.0:
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; RV64V-NEXT: vsetvli a0, zero, e16, m2, ta, mu
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; RV64V-NEXT: vfmv.v.f v8, fa0
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; RV64V-NEXT: ret
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%head = insertelement <vscale x 8 x half> undef, half %f, i32 0
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%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
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ret <vscale x 8 x half> %splat
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}
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define <vscale x 8 x half> @vsplat_zero_nxv8f16() {
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; RV32V-LABEL: vsplat_zero_nxv8f16:
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; RV32V: # %bb.0:
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; RV32V-NEXT: vsetvli a0, zero, e16, m2, ta, mu
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; RV32V-NEXT: vmv.v.i v8, 0
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; RV32V-NEXT: ret
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;
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; RV64V-LABEL: vsplat_zero_nxv8f16:
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; RV64V: # %bb.0:
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; RV64V-NEXT: vsetvli a0, zero, e16, m2, ta, mu
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; RV64V-NEXT: vmv.v.i v8, 0
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; RV64V-NEXT: ret
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%head = insertelement <vscale x 8 x half> undef, half zeroinitializer, i32 0
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%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
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ret <vscale x 8 x half> %splat
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}
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define <vscale x 8 x float> @vsplat_nxv8f32(float %f) {
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; RV32V-LABEL: vsplat_nxv8f32:
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; RV32V: # %bb.0:
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; RV32V-NEXT: vsetvli a0, zero, e32, m4, ta, mu
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; RV32V-NEXT: vfmv.v.f v8, fa0
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; RV32V-NEXT: ret
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;
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; RV64V-LABEL: vsplat_nxv8f32:
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; RV64V: # %bb.0:
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; RV64V-NEXT: vsetvli a0, zero, e32, m4, ta, mu
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; RV64V-NEXT: vfmv.v.f v8, fa0
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; RV64V-NEXT: ret
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%head = insertelement <vscale x 8 x float> undef, float %f, i32 0
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%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
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ret <vscale x 8 x float> %splat
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}
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define <vscale x 8 x float> @vsplat_zero_nxv8f32() {
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; RV32V-LABEL: vsplat_zero_nxv8f32:
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; RV32V: # %bb.0:
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; RV32V-NEXT: vsetvli a0, zero, e32, m4, ta, mu
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; RV32V-NEXT: vmv.v.i v8, 0
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; RV32V-NEXT: ret
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;
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; RV64V-LABEL: vsplat_zero_nxv8f32:
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; RV64V: # %bb.0:
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; RV64V-NEXT: vsetvli a0, zero, e32, m4, ta, mu
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; RV64V-NEXT: vmv.v.i v8, 0
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; RV64V-NEXT: ret
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%head = insertelement <vscale x 8 x float> undef, float zeroinitializer, i32 0
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%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
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ret <vscale x 8 x float> %splat
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}
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define <vscale x 8 x double> @vsplat_nxv8f64(double %f) {
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; RV32V-LABEL: vsplat_nxv8f64:
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; RV32V: # %bb.0:
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; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
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; RV32V-NEXT: vfmv.v.f v8, fa0
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; RV32V-NEXT: ret
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;
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; RV64V-LABEL: vsplat_nxv8f64:
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; RV64V: # %bb.0:
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; RV64V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
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; RV64V-NEXT: vfmv.v.f v8, fa0
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; RV64V-NEXT: ret
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%head = insertelement <vscale x 8 x double> undef, double %f, i32 0
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%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
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ret <vscale x 8 x double> %splat
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}
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define <vscale x 8 x double> @vsplat_zero_nxv8f64() {
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; RV32V-LABEL: vsplat_zero_nxv8f64:
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; RV32V: # %bb.0:
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; RV32V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
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; RV32V-NEXT: vmv.v.i v8, 0
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; RV32V-NEXT: ret
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;
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; RV64V-LABEL: vsplat_zero_nxv8f64:
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; RV64V: # %bb.0:
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; RV64V-NEXT: vsetvli a0, zero, e64, m8, ta, mu
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; RV64V-NEXT: vmv.v.i v8, 0
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; RV64V-NEXT: ret
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%head = insertelement <vscale x 8 x double> undef, double zeroinitializer, i32 0
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%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
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ret <vscale x 8 x double> %splat
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}
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