forked from OSchip/llvm-project
33 lines
1.4 KiB
LLVM
33 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64
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; This test checks a regression in the select-to-sra transform, which was
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; asserting (without a precondition) when the vector constants implicitly
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; truncated their inputs, as we do on RV64.
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define <4 x i32> @vselect_of_consts(<4 x i1> %cc) {
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; RV32-LABEL: vselect_of_consts:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a0, 284280
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; RV32-NEXT: addi a0, a0, 291
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; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
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; RV32-NEXT: vmv.v.x v25, a0
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; RV32-NEXT: lui a0, 214376
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; RV32-NEXT: addi a0, a0, -2030
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; RV32-NEXT: vmerge.vxm v8, v25, a0, v0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: vselect_of_consts:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a0, 284280
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; RV64-NEXT: addiw a0, a0, 291
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; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
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; RV64-NEXT: vmv.v.x v25, a0
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; RV64-NEXT: lui a0, 214376
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; RV64-NEXT: addiw a0, a0, -2030
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; RV64-NEXT: vmerge.vxm v8, v25, a0, v0
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; RV64-NEXT: ret
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%v = select <4 x i1> %cc, <4 x i32> <i32 878082066, i32 878082066, i32 878082066, i32 878082066>, <4 x i32> <i32 1164411171, i32 1164411171, i32 1164411171, i32 1164411171>
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ret <4 x i32> %v
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}
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