forked from OSchip/llvm-project
32 lines
1.4 KiB
LLVM
32 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=riscv64 -mattr=+experimental-zbb,+experimental-v \
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; RUN: -riscv-v-vector-bits-min=128 | FileCheck %s
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; This test loads to values and stores them in reversed order. This previously
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; asserted because part of DAGCombiner::tryStoreMerge thinks we can use an i64
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; rotate, but the loads aren't sufficiently aligned. So then it tried to use
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; a vector type, but that can't handle the swapped case.
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@foo = global [2 x i32] zeroinitializer, align 4
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@bar = global [2 x i32] zeroinitializer, align 4
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define void @baz() nounwind {
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; CHECK-LABEL: baz:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lui a0, %hi(foo)
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; CHECK-NEXT: addi a1, a0, %lo(foo)
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; CHECK-NEXT: lw a1, 4(a1)
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; CHECK-NEXT: lw a0, %lo(foo)(a0)
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; CHECK-NEXT: lui a2, %hi(bar)
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; CHECK-NEXT: sw a1, %lo(bar)(a2)
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; CHECK-NEXT: addi a1, a2, %lo(bar)
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; CHECK-NEXT: sw a0, 4(a1)
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; CHECK-NEXT: ret
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entry:
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%0 = load i32, i32* getelementptr inbounds ([2 x i32], [2 x i32]* @foo, i64 0, i64 1), align 4
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store i32 %0, i32* getelementptr inbounds ([2 x i32], [2 x i32]* @bar, i64 0, i64 0), align 4
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%1 = load i32, i32* getelementptr inbounds ([2 x i32], [2 x i32]* @foo, i64 0, i64 0), align 4
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store i32 %1, i32* getelementptr inbounds ([2 x i32], [2 x i32]* @bar, i64 0, i64 1), align 4
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ret void
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}
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